From: Nazim Amirul Agilex5 and other SoCFPGA platforms can wire per-DMA-channel TX/RX completion interrupts through the GIC as named platform IRQs. The common stmmac platform code already parses "tx-queue-N" / "rx-queue-N". Follow the same approach as dwmac-s32: if all configured TX and RX queue IRQs are present, set STMMAC_FLAG_MULTI_MSI_EN so the existing multi-IRQ request path and INTM=1 programming are used. Otherwise keep the single macirq path. Signed-off-by: Nazim Amirul --- .../ethernet/stmicro/stmmac/dwmac-socfpga.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c index 1d7f0a57d288..0e02f80aafee 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c @@ -593,6 +593,35 @@ static void socfpga_agilex5_setup_plat_dat(struct socfpga_dwmac *dwmac) plat_dat->crosststamp = smtg_crosststamp; } +static void socfpga_dwmac_setup_multi_irq(struct device *dev, + struct plat_stmmacenet_data *plat, + struct stmmac_resources *res) +{ + int i; + + for (i = 0; i < plat->rx_queues_to_use; i++) { + if (res->rx_irq[i] <= 0) { + dev_dbg(dev, "Missing RX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + for (i = 0; i < plat->tx_queues_to_use; i++) { + if (res->tx_irq[i] <= 0) { + dev_dbg(dev, "Missing TX queue %d interrupt\n", i); + goto mac_irq_mode; + } + } + + plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; + dev_info(dev, "Multi-IRQ mode (per queue IRQs) selected\n"); + return; + +mac_irq_mode: + plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; + dev_dbg(dev, "MAC IRQ mode selected\n"); +} + static int socfpga_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; @@ -652,6 +681,8 @@ static int socfpga_dwmac_probe(struct platform_device *pdev) ops->setup_plat_dat(dwmac); + socfpga_dwmac_setup_multi_irq(dev, plat_dat, &stmmac_res); + return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res); } -- 2.43.7