From: Lad Prabhakar Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so the driver can either perform the traditional global unlock sequence (as used on RZ/N1) or use a different policy for other SoCs (for example RZ/T2H, which does not require leaving registers unlocked). miic_reg_writel() now calls the per-SoC miic_write callback to perform register writes. Provide miic_reg_writel_unlocked() as the default writer and set it for the RZ/N1 OF data so existing platforms keep the same behaviour. Add a miic_unlock_regs() helper that implements the accessory register unlock sequence so the unlock/lock sequence can be reused where needed (for example when a SoC requires explicit unlock/lock around individual accesses). This change is preparatory work for supporting RZ/T2H. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang --- v2->v3: - Dropped inlining of miic_unlock_regs(). - Fixed checkpatch warning to fit within 80 columns. - Added Tested-by tag. v1->v2: - No change. --- drivers/net/pcs/pcs-rzn1-miic.c | 29 ++++++++++++++++++++++++----- 1 file changed, 24 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c index 75009b30084a..ef10994d8c11 100644 --- a/drivers/net/pcs/pcs-rzn1-miic.c +++ b/drivers/net/pcs/pcs-rzn1-miic.c @@ -155,6 +155,9 @@ struct miic { * @sw_mode_mask: Switch mode mask * @reset_ids: Reset names array * @reset_count: Number of entries in the reset_ids array + * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked + * before access. + * @miic_write: Function pointer to write a value to a MIIC register */ struct miic_of_data { struct modctrl_match *match_table; @@ -169,6 +172,8 @@ struct miic_of_data { u8 sw_mode_mask; const char * const *reset_ids; u8 reset_count; + bool init_unlock_lock_regs; + void (*miic_write)(struct miic *miic, int offset, u32 value); }; /** @@ -190,11 +195,25 @@ static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs) return container_of(pcs, struct miic_port, pcs); } -static void miic_reg_writel(struct miic *miic, int offset, u32 value) +static void miic_unlock_regs(struct miic *miic) +{ + /* Unprotect register writes */ + writel(0x00A5, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); + writel(0xFFFE, miic->base + MIIC_PRCMD); + writel(0x0001, miic->base + MIIC_PRCMD); +} + +static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value) { writel(value, miic->base + offset); } +static void miic_reg_writel(struct miic *miic, int offset, u32 value) +{ + miic->of_data->miic_write(miic, offset, value); +} + static u32 miic_reg_readl(struct miic *miic, int offset) { return readl(miic->base + offset); @@ -421,10 +440,8 @@ static int miic_init_hw(struct miic *miic, u32 cfg_mode) * is going to be used in conjunction with the Cortex-M3, this sequence * will have to be moved in register write */ - miic_reg_writel(miic, MIIC_PRCMD, 0x00A5); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); - miic_reg_writel(miic, MIIC_PRCMD, 0xFFFE); - miic_reg_writel(miic, MIIC_PRCMD, 0x0001); + if (miic->of_data->init_unlock_lock_regs) + miic_unlock_regs(miic); /* TODO: Replace with FIELD_PREP() when compile-time constant * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask. @@ -645,6 +662,8 @@ static struct miic_of_data rzn1_miic_of_data = { .miic_port_start = 1, .miic_port_max = 5, .sw_mode_mask = GENMASK(4, 0), + .init_unlock_lock_regs = true, + .miic_write = miic_reg_writel_unlocked, }; static const struct of_device_id miic_of_mtable[] = { -- 2.51.0