Drop the clock rate suffix from the NSS Clock Controller clock names for PPE and NSS clocks. A generic name allows for easier extension of support to additional SoCs that utilize same hardware design. Signed-off-by: Luo Jie --- .../devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml index 17252b6ea3be..b9ca69172adc 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-nsscc.yaml @@ -25,8 +25,8 @@ properties: clocks: items: - description: Board XO source - - description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source - - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source + - description: CMN_PLL NSS (Bias PLL cc) clock source + - description: CMN_PLL PPE (Bias PLL ubi nc) clock source - description: GCC GPLL0 OUT AUX clock source - description: Uniphy0 NSS Rx clock source - description: Uniphy0 NSS Tx clock source @@ -42,8 +42,8 @@ properties: clock-names: items: - const: xo - - const: nss_1200 - - const: ppe_353 + - const: nss + - const: ppe - const: gpll0_out - const: uniphy0_rx - const: uniphy0_tx @@ -82,8 +82,8 @@ examples: <&uniphy 5>, <&gcc GCC_NSSCC_CLK>; clock-names = "xo", - "nss_1200", - "ppe_353", + "nss", + "ppe", "gpll0_out", "uniphy0_rx", "uniphy0_tx", -- 2.34.1