Configure MSR intercepts for extended LVT registers when both AVIC and AVIC_EXTLVT are supported by hardware. Extended LVT registers are x2APIC MSRs at offsets 0x500-0x530 in the APIC register space. When AVIC is enabled and MSR intercepts are disabled, allow passthrough access to extended LVT MSRs. Hardware accelerates reads without VM-exits, while writes trigger trap-style VM-exits that are handled by the existing avic_unaccelerated_access_interception() path. Enable AVIC_EXTLVT support only when both X86_FEATURE_AVIC and X86_FEATURE_AVIC_EXTLVT are present. Signed-off-by: Manali Shukla --- arch/x86/kvm/svm/avic.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index f92214b1a938..039cb02dc00f 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -107,6 +107,7 @@ static bool next_vm_id_wrapped = 0; static DEFINE_SPINLOCK(svm_vm_data_hash_lock); static bool x2avic_enabled; static u32 x2avic_max_physical_id; +static bool avic_extlvt_enabled; static void avic_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept) @@ -155,6 +156,12 @@ static void avic_set_x2apic_msr_interception(struct vcpu_svm *svm, svm_set_intercept_for_msr(&svm->vcpu, x2avic_passthrough_msrs[i], MSR_TYPE_RW, intercept); + if (avic_extlvt_enabled) { + for (i = 0; i < svm->vcpu.kvm->arch.nr_extlvt; i++) + svm_set_intercept_for_msr(&svm->vcpu, X2APIC_MSR(APIC_EILVTn(i)), + MSR_TYPE_RW, intercept); + } + svm->x2avic_msrs_intercepted = intercept; } @@ -815,6 +822,10 @@ int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu) AVIC_UNACCEL_ACCESS_WRITE_MASK; bool trap = is_avic_unaccelerated_access_trap(offset); + if (avic_extlvt_enabled && + kvm_is_extlvt_offset(offset, vcpu->kvm->arch.nr_extlvt)) + trap = true; + trace_kvm_avic_unaccelerated_access(vcpu->vcpu_id, offset, trap, write, vector); if (trap) { @@ -1293,6 +1304,9 @@ bool __init avic_hardware_setup(void) */ enable_ipiv = enable_ipiv && boot_cpu_data.x86 != 0x17; + avic_extlvt_enabled = (boot_cpu_has(X86_FEATURE_AVIC) && + boot_cpu_has(X86_FEATURE_AVIC_EXTLVT)); + amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier); return true; -- 2.43.0