Enable the ST21NFCD on i2c9 (0x08), IRQ TLMM 41, reset TLMM 38 active-high. Compatible is st,st21nfcd (raw NCI). SYS_CLK is LN_BB_CLK2. VPS_IO is L18B (vreg_l18b). ese-present and uicc-present follow the public schematic (NFC_SWP1/SWP2: SWP_SE to SIM1, SWP_UICC to SIM2). Reader path is tested; SE/HCE is not. Signed-off-by: Kristian Brox --- arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts | 34 +++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts index 04cb9230d..ef66079a0 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-fairphone-fp5.dts @@ -908,7 +908,23 @@ redriver_ss_in: endpoint { &i2c9 { status = "okay"; - /* ST21NFC NFC @ 28 */ + nfc@8 { + compatible = "st,st21nfcd"; + reg = <0x08>; + + interrupts-extended = <&tlmm 41 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&tlmm 38 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&nfc_default>; + pinctrl-names = "default"; + + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; + vdd-io-supply = <&vreg_l18b>; + + ese-present; + uicc-present; + }; + /* VL53L3 ToF @ 29 */ }; @@ -1410,6 +1426,22 @@ hall_sensor_default: hall-sensor-default-state { drive-strength = <2>; bias-pull-up; }; + + nfc_default: nfc-default-state { + reset-pins { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + int-pins { + pins = "gpio41"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + }; }; &uart5 { -- 2.55.0