Add support for JHB100 System-2 clock generator (SYS2CRG). Signed-off-by: Changhuang Liang --- drivers/clk/starfive/Kconfig | 8 + drivers/clk/starfive/Makefile | 1 + .../clk/starfive/clk-starfive-jhb100-sys2.c | 178 ++++++++++++++++++ 3 files changed, 187 insertions(+) create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig index b6042bcb5992..729bdfce7b8a 100644 --- a/drivers/clk/starfive/Kconfig +++ b/drivers/clk/starfive/Kconfig @@ -91,3 +91,11 @@ config CLK_STARFIVE_JHB100_SYS1 help Say yes here to support the system-1 clock controller on the StarFive JHB100 SoC. + +config CLK_STARFIVE_JHB100_SYS2 + bool "StarFive JHB100 system-2 clock support" + depends on CLK_STARFIVE_JHB100_SYS0 + default ARCH_STARFIVE + help + Say yes here to support the system-2 clock controller on the + StarFive JHB100 SoC. diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile index b3571e2f0555..90b6390296bd 100644 --- a/drivers/clk/starfive/Makefile +++ b/drivers/clk/starfive/Makefile @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c new file mode 100644 index 000000000000..5111f139a1c3 --- /dev/null +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c @@ -0,0 +1,178 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * StarFive JHB100 System-2 Clock Driver + * + * Copyright (C) 2024 StarFive Technology Co., Ltd. + * + * Author: Changhuang Liang + * + */ + +#include +#include +#include +#include +#include + +#include "clk-starfive-jhb100.h" + +#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1) + +/* external clocks */ +#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0) +#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1) +#define JHB100_SYS2CLK_GPU0_600 (JHB100_SYS2CLK_NUM_CLKS + 2) +#define JHB100_SYS2CLK_GPU1_600 (JHB100_SYS2CLK_NUM_CLKS + 3) + +static const struct starfive_clk_data jhb100_sys2crg_clk_data[] __initconst = { + /* jtag mst*/ + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_200, "jtagm0_200", 6, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_200, "jtagm1_200", 6, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_100, "jtagm0_100", 12, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_100, "jtagm1_100", 12, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM0_100), + STARFIVE__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2, + JHB100_SYS2CLK_JTAGM1_100), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_200), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_100), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_200), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100), + STARFIVE_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock", + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_100), + /* hostusbcmn */ + STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSB_100, "hostusb_100", 12, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_HOSTUSBCMN_500, "hostusbcmn_500", 4, + JHB100_SYS2CLK_PLL1), + /* bmcperiph1 */ + STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_200, "bmcper1_200", 6, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_250, "bmcper1_250", 5, + JHB100_SYS2CLK_PLL1), + STARFIVE__DIV(JHB100_SYS2CLK_BMCPER1_143_DFT, "bmcper1_143_dft", 8, + JHB100_SYS2CLK_PLL1), + STARFIVE_GATE(JHB100_SYS2CLK_BMCPER1_143, "bmcper1_143", CLK_IS_CRITICAL, + JHB100_SYS2CLK_BMCPER1_143_DFT), + /* bmcperiph0 */ + STARFIVE__DIV(JHB100_SYS2CLK_BMCPER0_200, "bmcper0_200", 6, + JHB100_SYS2CLK_PLL1), + /* gpu0 */ + STARFIVE__DIV(JHB100_SYS2CLK_GPU0_100, "gpu0_100", 12, + JHB100_SYS2CLK_PLL1), + STARFIVE_GATE(JHB100_SYS2CLK_GPU0_BUS_CLK, "gpu0_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_600), + STARFIVE_GATE(JHB100_SYS2CLK_GPU0_APB_CLK, "gpu0_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU0_100), + STARFIVE_GATE(JHB100_SYS2CLK_GPU0_OSC_CLK, "gpu0_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* gpu1 */ + STARFIVE__DIV(JHB100_SYS2CLK_GPU1_100, "gpu1_100", 12, + JHB100_SYS2CLK_PLL1), + STARFIVE_GATE(JHB100_SYS2CLK_GPU1_BUS_CLK, "gpu1_bus_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_600), + STARFIVE_GATE(JHB100_SYS2CLK_GPU1_APB_CLK, "gpu1_apb_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_GPU1_100), + STARFIVE_GATE(JHB100_SYS2CLK_GPU1_OSC_CLK, "gpu1_osc_clk", CLK_IS_CRITICAL, + JHB100_SYS2CLK_OSC), + /* main icg */ + STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG0, "main_icg_en_jtag0", 0, + JHB100_SYS2CLK_JTAGM0_200), + STARFIVE_GATE(JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1, "main_icg_en_jtag1", 0, + JHB100_SYS2CLK_JTAGM1_200), +}; + +static int __init jhb100_sys2crg_probe(struct platform_device *pdev) +{ + struct starfive_clk_priv *priv; + unsigned int idx; + int ret; + + priv = devm_kzalloc(&pdev->dev, + struct_size(priv, reg, JHB100_SYS2CLK_NUM_CLKS), + GFP_KERNEL); + if (!priv) + return -ENOMEM; + + spin_lock_init(&priv->rmw_lock); + priv->num_reg = JHB100_SYS2CLK_NUM_CLKS; + priv->dev = &pdev->dev; + priv->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + for (idx = 0; idx < JHB100_SYS2CLK_NUM_CLKS; idx++) { + u32 max = jhb100_sys2crg_clk_data[idx].max; + struct clk_parent_data parents[4] = {}; + struct clk_init_data init = { + .name = jhb100_sys2crg_clk_data[idx].name, + .ops = starfive_clk_ops(max), + .parent_data = parents, + .num_parents = + ((max & STARFIVE_CLK_MUX_MASK) >> STARFIVE_CLK_MUX_SHIFT) + 1, + .flags = jhb100_sys2crg_clk_data[idx].flags, + }; + struct starfive_clk *clk = &priv->reg[idx]; + unsigned int i; + + if (!init.name) + continue; + + for (i = 0; i < init.num_parents; i++) { + unsigned int pidx = jhb100_sys2crg_clk_data[idx].parents[i]; + + if (pidx < JHB100_SYS2CLK_NUM_CLKS) + parents[i].hw = &priv->reg[pidx].hw; + else if (pidx == JHB100_SYS2CLK_OSC) + parents[i].fw_name = "osc"; + else if (pidx == JHB100_SYS2CLK_PLL1) + parents[i].fw_name = "pll1"; + else if (pidx == JHB100_SYS2CLK_GPU0_600) + parents[i].fw_name = "sys2_gpu0_600"; + else + parents[i].fw_name = "sys2_gpu1_600"; + } + + clk->hw.init = &init; + clk->idx = idx; + clk->max_div = max & STARFIVE_CLK_DIV_MASK; + + ret = devm_clk_hw_register(&pdev->dev, &clk->hw); + if (ret) + return ret; + } + + ret = devm_of_clk_add_hw_provider(&pdev->dev, starfive_clk_get, priv); + if (ret) + return ret; + + return jhb100_reset_controller_register(priv, "r-sys2", 0); +} + +static const struct of_device_id jhb100_sys2crg_match[] = { + { .compatible = "starfive,jhb100-sys2crg" }, + { /* sentinel */ } +}; + +static struct platform_driver jhb100_sys2crg_driver = { + .driver = { + .name = "clk-starfive-jhb100-sys2", + .of_match_table = jhb100_sys2crg_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver_probe(jhb100_sys2crg_driver, jhb100_sys2crg_probe); -- 2.25.1