Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter --- v5: no change v4: no change v3: no change v2: Remove #address-cells and #size-cells arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 51d00dac12de..b954952d962b 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -325,6 +325,11 @@ usdhc0-200mhz-grp4 { }; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g2-gpr", "syscon"; + reg = <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible = "nxp,s32g2-ocotp"; reg = <0x400a4000 0x400>; @@ -731,6 +736,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index e314f3c7d61d..be03db737384 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -383,6 +383,11 @@ usdhc0-200mhz-grp4 { }; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g3-gpr", "syscon"; + reg = <0x4007c000 0x3000>; + }; + ocotp: nvmem@400a4000 { compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp"; reg = <0x400a4000 0x400>; @@ -808,6 +813,7 @@ gmac0: ethernet@4033c000 { compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; -- 2.51.0