From: Irving-CH Lin Add support for the MT8189 cam clock controller, which provides clock gate control for camera. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 11 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-cam.c | 108 ++++++++++++++++++++++++++ 3 files changed, 120 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-cam.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 0e7fdb5421e6..82a26d952bff 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -839,6 +839,17 @@ config COMMON_CLK_MT8189_BUS MT8189 chipset, ensuring that all bus-related components receive the correct clock signals for optimal performance. +config COMMON_CLK_MT8189_CAM + tristate "Clock driver for MediaTek MT8189 cam" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock management for the camera interface + on MediaTek MT8189 SoCs. This includes enabling, disabling, and + setting the rate for camera-related clocks. If you have a camera + that relies on this SoC and you want to control its clocks, say Y or M + to include this driver in your kernel build. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index aabfb42cb1b2..95a8f4ae05ee 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -126,6 +126,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \ clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o +obj-$(CONFIG_COMMON_CLK_MT8189_CAM) += clk-mt8189-cam.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-cam.c b/drivers/clk/mediatek/clk-mt8189-cam.c new file mode 100644 index 000000000000..d65ac08cedd6 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-cam.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs cam_m_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM_M(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_m_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_m_clks[] = { + GATE_CAM_M(CLK_CAM_M_LARB13, "cam_m_larb13", "cam_sel", 0), + GATE_CAM_M(CLK_CAM_M_LARB14, "cam_m_larb14", "cam_sel", 2), + GATE_CAM_M(CLK_CAM_M_CAMSYS_MAIN_CAM, "cam_m_camsys_main_cam", "cam_sel", 6), + GATE_CAM_M(CLK_CAM_M_CAMSYS_MAIN_CAMTG, "cam_m_camsys_main_camtg", "cam_sel", 7), + GATE_CAM_M(CLK_CAM_M_SENINF, "cam_m_seninf", "cam_sel", 8), + GATE_CAM_M(CLK_CAM_M_CAMSV1, "cam_m_camsv1", "cam_sel", 10), + GATE_CAM_M(CLK_CAM_M_CAMSV2, "cam_m_camsv2", "cam_sel", 11), + GATE_CAM_M(CLK_CAM_M_CAMSV3, "cam_m_camsv3", "cam_sel", 12), + GATE_CAM_M(CLK_CAM_M_FAKE_ENG, "cam_m_fake_eng", "cam_sel", 17), + GATE_CAM_M(CLK_CAM_M_CAM2MM_GALS, "cam_m_cam2mm_gals", "cam_sel", 19), + GATE_CAM_M(CLK_CAM_M_CAMSV4, "cam_m_camsv4", "cam_sel", 20), + GATE_CAM_M(CLK_CAM_M_PDA, "cam_m_pda", "cam_sel", 21), +}; + +static const struct mtk_clk_desc cam_m_mcd = { + .clks = cam_m_clks, + .num_clks = ARRAY_SIZE(cam_m_clks), +}; + +static const struct mtk_gate_regs cam_ra_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM_RA(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_ra_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_ra_clks[] = { + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_LARBX, "cam_ra_camsys_rawa_larbx", "cam_sel", 0), + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_CAM, "cam_ra_camsys_rawa_cam", "cam_sel", 1), + GATE_CAM_RA(CLK_CAM_RA_CAMSYS_RAWA_CAMTG, "cam_ra_camsys_rawa_camtg", "cam_sel", 2), +}; + +static const struct mtk_clk_desc cam_ra_mcd = { + .clks = cam_ra_clks, + .num_clks = ARRAY_SIZE(cam_ra_clks), +}; + +static const struct mtk_gate_regs cam_rb_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_CAM_RB(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &cam_rb_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr, CLK_IGNORE_UNUSED) + +static const struct mtk_gate cam_rb_clks[] = { + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_LARBX, "cam_rb_camsys_rawb_larbx", "cam_sel", 0), + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_CAM, "cam_rb_camsys_rawb_cam", "cam_sel", 1), + GATE_CAM_RB(CLK_CAM_RB_CAMSYS_RAWB_CAMTG, "cam_rb_camsys_rawb_camtg", "cam_sel", 2), +}; + +static const struct mtk_clk_desc cam_rb_mcd = { + .clks = cam_rb_clks, + .num_clks = ARRAY_SIZE(cam_rb_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_cam[] = { + { .compatible = "mediatek,mt8189-camsys-main", .data = &cam_m_mcd }, + { .compatible = "mediatek,mt8189-camsys-rawa", .data = &cam_ra_mcd }, + { .compatible = "mediatek,mt8189-camsys-rawb", .data = &cam_rb_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_cam); + +static struct platform_driver clk_mt8189_cam_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-cam", + .of_match_table = of_match_clk_mt8189_cam, + }, +}; + +module_platform_driver(clk_mt8189_cam_drv); +MODULE_DESCRIPTION("MediaTek MT8189 cam clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2