In preparation for splitting the MDIO bus into a separate driver, convert all register reads/writes to use ioread32/iowrite32 directly instead of using the axienet_ior/iow helpers. While we're at it, clean up the register calculations a bit. Signed-off-by: Sean Anderson --- Changes in v3: - New .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 43 +++++++++---------- 1 file changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index 9ca2643c921e..16f3581390dd 100644 --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c @@ -32,7 +32,7 @@ static int axienet_mdio_wait_until_ready(struct axienet_local *lp) { u32 val; - return readx_poll_timeout(axinet_ior_read_mcr, lp, + return readx_poll_timeout(ioread32, lp->regs + XAE_MDIO_MCR_OFFSET, val, val & XAE_MDIO_MCR_READY_MASK, 1, 20000); } @@ -45,8 +45,8 @@ static int axienet_mdio_wait_until_ready(struct axienet_local *lp) */ static void axienet_mdio_mdc_enable(struct axienet_local *lp) { - axienet_iow(lp, XAE_MDIO_MC_OFFSET, - ((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK)); + iowrite32((u32)lp->mii_clk_div | XAE_MDIO_MC_MDIOEN_MASK, + lp->regs + XAE_MDIO_MC_OFFSET); } /** @@ -59,9 +59,9 @@ static void axienet_mdio_mdc_disable(struct axienet_local *lp) { u32 mc_reg; - mc_reg = axienet_ior(lp, XAE_MDIO_MC_OFFSET); - axienet_iow(lp, XAE_MDIO_MC_OFFSET, - (mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK)); + mc_reg = ioread32(lp->regs + XAE_MDIO_MC_OFFSET); + iowrite32(mc_reg & ~XAE_MDIO_MC_MDIOEN_MASK, + lp->regs + XAE_MDIO_MC_OFFSET); } /** @@ -90,13 +90,11 @@ static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg) return ret; } - axienet_iow(lp, XAE_MDIO_MCR_OFFSET, - (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) & - XAE_MDIO_MCR_PHYAD_MASK) | - ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & - XAE_MDIO_MCR_REGAD_MASK) | - XAE_MDIO_MCR_INITIATE_MASK | - XAE_MDIO_MCR_OP_READ_MASK)); + rc = FIELD_PREP(XAE_MDIO_MCR_PHYAD_MASK, phy_id) | + FIELD_PREP(XAE_MDIO_MCR_REGAD_MASK, reg) | + XAE_MDIO_MCR_INITIATE_MASK | + XAE_MDIO_MCR_OP_READ_MASK; + iowrite32(rc, lp->regs + XAE_MDIO_MCR_OFFSET); ret = axienet_mdio_wait_until_ready(lp); if (ret < 0) { @@ -104,7 +102,7 @@ static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg) return ret; } - rc = axienet_ior(lp, XAE_MDIO_MRD_OFFSET) & 0x0000FFFF; + rc = ioread32(lp->regs + XAE_MDIO_MRD_OFFSET) & 0x0000FFFF; dev_dbg(lp->dev, "axienet_mdio_read(phy_id=%i, reg=%x) == %x\n", phy_id, reg, rc); @@ -129,8 +127,9 @@ static int axienet_mdio_read(struct mii_bus *bus, int phy_id, int reg) static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val) { - int ret; struct axienet_local *lp = bus->priv; + int ret; + u32 mcr; dev_dbg(lp->dev, "axienet_mdio_write(phy_id=%i, reg=%x, val=%x)\n", phy_id, reg, val); @@ -143,14 +142,12 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg, return ret; } - axienet_iow(lp, XAE_MDIO_MWD_OFFSET, (u32)val); - axienet_iow(lp, XAE_MDIO_MCR_OFFSET, - (((phy_id << XAE_MDIO_MCR_PHYAD_SHIFT) & - XAE_MDIO_MCR_PHYAD_MASK) | - ((reg << XAE_MDIO_MCR_REGAD_SHIFT) & - XAE_MDIO_MCR_REGAD_MASK) | - XAE_MDIO_MCR_INITIATE_MASK | - XAE_MDIO_MCR_OP_WRITE_MASK)); + iowrite32(val, lp->regs + XAE_MDIO_MWD_OFFSET); + mcr = FIELD_PREP(XAE_MDIO_MCR_PHYAD_MASK, phy_id) | + FIELD_PREP(XAE_MDIO_MCR_REGAD_MASK, reg) | + XAE_MDIO_MCR_INITIATE_MASK | + XAE_MDIO_MCR_OP_WRITE_MASK; + iowrite32(mcr, lp->regs + XAE_MDIO_MCR_OFFSET); ret = axienet_mdio_wait_until_ready(lp); if (ret < 0) { -- 2.35.1.1320.gc452695387.dirty