From: Tina Zhang When x-vendor-cpuid-only is enabled, QEMU suppresses CPUID leaves 2 and 4 for AuthenticAMD CPUs because those leaves describe Intel cache information. Hygon Dhyana uses the HygonGenuine vendor string, so it currently skips that filtering and can expose Intel cache leaves together with AMD/Hygon extended cache leaves. That is inconsistent guest-visible CPUID: Hygon Dhyana provides cache information through the extended cache leaves, so it should not also advertise the Intel cache descriptor and deterministic cache parameter leaves. Apply the same leaf 2 and leaf 4 filtering to Hygon CPUs when Hygon vendor ABI fixes are enabled. The property keeps the old CPUID output for pc-11.0 and older machine types. Signed-off-by: Tina Zhang --- target/i386/cpu.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 32b8bc9ebd..f0cad38c94 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -8622,6 +8622,21 @@ static bool x86_cpu_has_amd_cpuid_aliases(const X86CPU *cpu) (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env)); } +/* + * CPUID leaves 2 and 4 describe Intel cache information. AMD CPUs use + * extended cache leaves instead, and Hygon Dhyana follows that AMD/Hygon + * convention. Enable the corrected Hygon behavior only for machine types + * where Hygon vendor ABI fixes are on. + */ +static bool x86_cpu_filter_intel_cache_leaves(const X86CPU *cpu) +{ + const CPUX86State *env = &cpu->env; + + return cpu->vendor_cpuid_only && + (IS_AMD_CPU(env) || + (cpu->hygon_vendor_abi_fixes && IS_HYGON_CPU(env))); +} + void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) @@ -8707,7 +8722,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax = *ebx = *ecx = *edx = 0; break; } @@ -8743,7 +8758,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, CPU_TOPOLOGY_LEVEL_SOCKET), 4095) << 14; } } - } else if (cpu->vendor_cpuid_only && IS_AMD_CPU(env)) { + } else if (x86_cpu_filter_intel_cache_leaves(cpu)) { *eax = *ebx = *ecx = *edx = 0; } else { *eax = 0; -- 2.43.7