Add the gp_mn pin mux function on gpio32 of QCS8300. This exposes the GP M/N divider clock output on the dedicated GPIO pin. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/pinctrl/qcom/pinctrl-qcs8300.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-qcs8300.c b/drivers/pinctrl/qcom/pinctrl-qcs8300.c index fec86818c51188a0949e268382fb0c5de3f66f1a..349369fcdf18342b27067b91414eacbe378224e7 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs8300.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs8300.c @@ -424,6 +424,7 @@ enum qcs8300_functions { msm_mux_gcc_gp3, msm_mux_gcc_gp4, msm_mux_gcc_gp5, + msm_mux_gp_mn, msm_mux_hs0_mi2s, msm_mux_hs1_mi2s, msm_mux_hs2_mi2s, @@ -651,6 +652,10 @@ static const char *const gcc_gp5_groups[] = { "gpio76", "gpio77", }; +static const char *const gp_mn_groups[] = { + "gpio32", +}; + static const char * const hs0_mi2s_groups[] = { "gpio106", "gpio107", "gpio108", "gpio109", }; @@ -955,6 +960,7 @@ static const struct pinfunction qcs8300_functions[] = { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gp_mn), MSM_PIN_FUNCTION(hs0_mi2s), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), @@ -1062,7 +1068,8 @@ static const struct msm_pingroup qcs8300_groups[] = { [30] = PINGROUP(30, qup0_se4, cci_i2c_scl, cci_async, emac0_ptp_pps, tgu_ch3, _, _, _, _, _, _), [31] = PINGROUP(31, qup0_se4, cci_i2c_sda, cci_async, emac0_ptp_aux, _, _, _, _, _, _, _), - [32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, _, _, _, _, _, _, _), + [32] = PINGROUP(32, qup0_se4, cci_i2c_scl, emac0_ptp_aux, mdp_vsync, gp_mn, _, _, _, _, + _, _), [33] = PINGROUP(33, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), [34] = PINGROUP(34, qup0_se2, qdss_gpio, _, _, _, _, _, _, _, _, _), [35] = PINGROUP(35, qup0_se2, gcc_gp1, _, _, _, _, _, _, _, _, _), -- 2.34.1