Add the netc_iep18 PCIe ECAM host node describing the NETC integrated endpoint bus allocated to the first Linux cohort on S32N79. The bus is enumerated via the generic pci-host-ecam-generic driver and hosts the ENETC v4 Pseudo-MAC (PPM) PF and its VFs, which connect internally to the on-chip NETC switch (not owned by Linux). The node is kept disabled at the SoC level; boards that wire up NETC enable it. MSIs are routed through the GIC-v3 ITS (msi-map) and DMA is translated by the SMMUv3 (iommu-map). Signed-off-by: Claudiu Manoil --- v3: none v2: - Replaced the 'msi-parent' stub property with 'msi-map', as per H/W spec. arch/arm64/boot/dts/freescale/s32n79.dtsi | 24 +++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32n79.dtsi b/arch/arm64/boot/dts/freescale/s32n79.dtsi index 94ab58783fdc8..65cf65e828328 100644 --- a/arch/arm64/boot/dts/freescale/s32n79.dtsi +++ b/arch/arm64/boot/dts/freescale/s32n79.dtsi @@ -122,6 +122,30 @@ irqsteer_coss: interrupt-controller@4ed00000 { }; }; + nwss-bus { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x48800000 0x0 0x48800000 0x0 0x4b0000>, + <0x2 0x40000000 0x2 0x40000000 0x0 0x20000000>; + + netc_iep18: pcie@241200000 { + compatible = "pci-host-ecam-generic"; + reg = <0x2 0x41200000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0x0>; + iommu-map = <0x0 &smmu 0xc0000 0x100>; + msi-map = <0x0 &its 0xc0000 0x100>; + dma-coherent; + status = "disabled"; + + /* All NETC PCIe functions */ + ranges = <0x82000000 0x0 0x48800000 0x0 0x48800000 0x0 0x4b0000>; + }; + }; + cpus { #address-cells = <1>; #size-cells = <0>; -- 2.34.1