If we have RASv1p1 on the host, advertise it to the guest in the "canonical way", by setting ID_AA64PFR0_EL1 to V1P1, rather than the convoluted RAS+RAS_frac method. Note that this also advertises FEAT_DoubleFault, which doesn't affect the guest at all, as only EL3 is concerned by this. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 1b4114790024e..66e5a733e9628 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1800,6 +1800,18 @@ static u64 sanitise_id_aa64pfr0_el1(const struct kvm_vcpu *vcpu, u64 val) if (!vcpu_has_sve(vcpu)) val &= ~ID_AA64PFR0_EL1_SVE_MASK; + /* + * Describe RASv1p1 in a canonical way -- ID_AA64PFR1_EL1.RAS_frac + * is cleared separately. Note that by advertising RASv1p1 here, we + * implicitly advertise FEAT_DoubleFault. However, since that last + * feature is a pure EL3 feature, this is not relevant for the + * guest, and we save on the complexity. + */ + if (cpus_have_final_cap(ARM64_HAS_RASV1P1_EXTN)) { + val &= ~ID_AA64PFR0_EL1_RAS; + val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, V1P1); + } + /* * The default is to expose CSV2 == 1 if the HW isn't affected. * Although this is a per-CPU feature, we make it global because -- 2.39.2