From: Zhi Li Enable the on-board Gigabit Ethernet controller on the HiFive Premier P550 development board. Signed-off-by: Zhi Li --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 239 ++++++++++++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 105 ++++++++ 2 files changed, 344 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 131ed1fc6b2e..4e09ad738d3d 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -13,11 +13,250 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { stdout-path = "serial0:115200n8"; }; + + vcc_1v8: vcc1v8 { + compatible = "regulator-fixed"; + regulator-name = "vcc1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; +}; + +&xtal24m { + clock-frequency = <24000000>; + clock-output-names = "xtal24m"; +}; + +&pinctrl { + status = "okay"; + vrgmii-supply = <&vcc_1v8>; + + pinctrl_gpio0: gpio0-grp { + gpio0-pins { + pins = "gpio0"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + pinctrl_gpio5: gpio5-grp { + gpio5-pins { + pins = "gpio5"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + pinctrl_gpio11: gpio11-grp { + gpio11-pins { + pins = "gpio11"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + pinctrl_gpio14: gpio14-grp { + gpio14-pins { + pins = "mode_set1"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio15: gpio15-grp { + gpio15-pins { + pins = "mode_set2"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + pinctrl_gpio28: gpio28-grp { + gpio28-pins { + pins = "gpio28"; + function = "gpio"; + input-enable; + bias-disable; + }; + }; + + pinctrl_gpio43: gpio43-grp { + gpio43-pins { + pins = "usb1_pwren"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio71: gpio71-grp { + gpio71-pins { + pins = "mipi_csi0_xhs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio74: gpio74-grp { + gpio74-pins { + pins = "mipi_csi1_xhs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio76: gpio76-grp { + gpio76-pins { + pins = "mipi_csi2_xvs"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio77: gpio77-grp { + gpio77-pins { + pins = "mipi_csi2_xhs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio79: gpio79-grp { + gpio79-pins { + pins = "mipi_csi3_xvs"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio80: gpio80-grp { + gpio80-pins { + pins = "mipi_csi3_xhs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio82: gpio82-grp { + gpio82-pins { + pins = "mipi_csi4_xvs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio84: gpio84-grp { + gpio84-pins { + pins = "mipi_csi4_mclk"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio85: gpio85-grp { + gpio85-pins { + pins = "mipi_csi5_xvs"; + function = "gpio"; + input-disable; + bias-pull-up; + }; + }; + + pinctrl_gpio94: gpio94-grp { + gpio94-pins { + pins = "s_mode"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio106: gpio106-grp { + gpio106-pins { + pins = "gpio106"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; + + pinctrl_gpio111: gpio111-grp { + gpio111-pins { + pins = "gpio111"; + function = "gpio"; + input-disable; + bias-disable; + }; + }; +}; + +&gmac0 { + phy-handle = <&gmac0_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio106>; + rx-internal-delay-ps = <20>; + tx-internal-delay-ps = <100>; + status = "okay"; +}; + +&gmac0_mdio { + gmac0_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; +}; + +&gmac1 { + phy-handle = <&gmac1_phy0>; + /* + * For the TX path of gmac1, there is a skew between the TX clock + * and data on the MAC controller inside the silicon. This skew happens + * to be approximately 2 ns. Therefore, it can be considered that the + * 2 ns delay of TX is provided by the MAC. + * No delay configuration for tx is needed in software via PHY driver. + */ + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio111>; + rx-internal-delay-ps = <200>; + tx-internal-delay-ps = <200>; + status = "okay"; +}; + +&gmac1_mdio { + gmac1_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-gpios = <&gpioD 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; }; &uart0 { diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index c3ed93008bca..c77bc8b1b7bc 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -5,6 +5,9 @@ /dts-v1/; +#include +#include + / { #address-cells = <2>; #size-cells = <2>; @@ -202,6 +205,11 @@ pmu { <0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>; }; + xtal24m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; ranges; @@ -245,6 +253,85 @@ plic: interrupt-controller@c000000 { #interrupt-cells = <1>; }; + hsp_power_domain: bus@50400000 { + compatible = "simple-pm-bus"; + ranges; + clocks = <&clk 171>; + #address-cells = <2>; + #size-cells = <2>; + + hsp_sp_csr: hsp-sp-top-csr@50440000 { + compatible = "eswin,eic7700-syscfg", "syscon"; + reg = <0x0 0x50440000 0x0 0x2000>; + }; + + gmac0: ethernet@50400000 { + compatible = "eswin,eic7700-qos-eth", + "snps,dwmac-5.20"; + reg = <0x0 0x50400000 0x0 0x10000>; + interrupts = <61>; + interrupt-names = "macirq"; + clocks = <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 193>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset EIC7700_RESET_HSP_ETH0_ARST>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x118 0x114 0x11c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac0>; + status = "disabled"; + + gmac0_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + stmmac_axi_setup_gmac0: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; + + gmac1: ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth-clk-inversion", + "snps,dwmac-5.20"; + reg = <0x0 0x50410000 0x0 0x10000>; + interrupts = <70>; + interrupt-names = "macirq"; + clocks = <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 194>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset EIC7700_RESET_HSP_ETH1_ARST>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x218 0x214 0x21c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac1>; + status = "disabled"; + + gmac1_mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + }; + + stmmac_axi_setup_gmac1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; + }; + uart0: serial@50900000 { compatible = "snps,dw-apb-uart"; reg = <0x0 0x50900000 0x0 0x10000>; @@ -341,5 +428,23 @@ gpioD: gpio-port@3 { #gpio-cells = <2>; }; }; + + pinctrl: pinctrl@51600080 { + compatible = "eswin,eic7700-pinctrl"; + reg = <0x0 0x51600080 0x0 0x1fff80>; + }; + + clk: clock-controller@51828000 { + compatible = "eswin,eic7700-clock"; + reg = <0x0 0x51828000 0x0 0x300>; + clocks = <&xtal24m>; + #clock-cells = <1>; + }; + + reset: reset-controller@51828300 { + compatible = "eswin,eic7700-reset"; + reg = <0x0 0x51828300 0x0 0x200>; + #reset-cells = <1>; + }; }; }; -- 2.25.1