Rather than providing a now-empty set_to_rmii() method to indicate that RMII is supported, switch to setting ops->supports_rmii instead. Signed-off-by: Russell King (Oracle) --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 86 ++++++------------- 1 file changed, 24 insertions(+), 62 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c index fbc0e50519f6..c9a915b2cb84 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -241,12 +241,7 @@ static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, #define PX30_GRF_GMAC_CON1 0x0904 -static void px30_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops px30_ops = { - .set_to_rmii = px30_set_to_rmii, .set_speed = rk_set_clk_mac_speed, .phy_intf_sel_grf_reg = PX30_GRF_GMAC_CON1, @@ -254,6 +249,8 @@ static const struct rk_gmac_ops px30_ops = { .speed_grf_reg = PX30_GRF_GMAC_CON1, .mac_speed_mask = BIT_U16(2), + + .supports_rmii = true, }; #define RK3128_GRF_MAC_CON0 0x0168 @@ -280,13 +277,8 @@ static void rk3128_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3128_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3128_ops = { .set_to_rgmii = rk3128_set_to_rgmii, - .set_to_rmii = rk3128_set_to_rmii, .phy_intf_sel_grf_reg = RK3128_GRF_MAC_CON1, .phy_intf_sel_mask = GENMASK_U16(8, 6), @@ -296,6 +288,8 @@ static const struct rk_gmac_ops rk3128_ops = { .gmii_clk_sel_mask = GENMASK_U16(13, 12), .rmii_clk_sel_mask = BIT_U16(11), .mac_speed_mask = BIT_U16(10), + + .supports_rmii = true, }; #define RK3228_GRF_MAC_CON0 0x0900 @@ -383,13 +377,8 @@ static void rk3288_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3288_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3288_ops = { .set_to_rgmii = rk3288_set_to_rgmii, - .set_to_rmii = rk3288_set_to_rmii, .phy_intf_sel_grf_reg = RK3288_GRF_SOC_CON1, .phy_intf_sel_mask = GENMASK_U16(8, 6), @@ -399,6 +388,8 @@ static const struct rk_gmac_ops rk3288_ops = { .gmii_clk_sel_mask = GENMASK_U16(13, 12), .rmii_clk_sel_mask = BIT_U16(11), .mac_speed_mask = BIT_U16(10), + + .supports_rmii = true, }; #define RK3308_GRF_MAC_CON0 0x04a0 @@ -407,18 +398,14 @@ static const struct rk_gmac_ops rk3288_ops = { #define RK3308_GMAC_FLOW_CTRL GRF_BIT(3) #define RK3308_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) -static void rk3308_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3308_ops = { - .set_to_rmii = rk3308_set_to_rmii, - .phy_intf_sel_grf_reg = RK3308_GRF_MAC_CON0, .phy_intf_sel_mask = GENMASK_U16(4, 2), .speed_grf_reg = RK3308_GRF_MAC_CON0, .mac_speed_mask = BIT_U16(0), + + .supports_rmii = true, }; #define RK3328_GRF_MAC_CON0 0x0900 @@ -470,10 +457,6 @@ static void rk3328_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3328_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) { regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, @@ -485,7 +468,6 @@ static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv) static const struct rk_gmac_ops rk3328_ops = { .init = rk3328_init, .set_to_rgmii = rk3328_set_to_rgmii, - .set_to_rmii = rk3328_set_to_rmii, .integrated_phy_powerup = rk3328_integrated_phy_powerup, .integrated_phy_powerdown = rk_gmac_integrated_ephy_powerdown, @@ -495,6 +477,8 @@ static const struct rk_gmac_ops rk3328_ops = { .rmii_clk_sel_mask = BIT_U16(7), .mac_speed_mask = BIT_U16(2), + .supports_rmii = true, + .regs_valid = true, .regs = { 0xff540000, /* gmac2io */ @@ -527,13 +511,8 @@ static void rk3366_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3366_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3366_ops = { .set_to_rgmii = rk3366_set_to_rgmii, - .set_to_rmii = rk3366_set_to_rmii, .phy_intf_sel_grf_reg = RK3366_GRF_SOC_CON6, .phy_intf_sel_mask = GENMASK_U16(11, 9), @@ -543,6 +522,8 @@ static const struct rk_gmac_ops rk3366_ops = { .gmii_clk_sel_mask = GENMASK_U16(5, 4), .rmii_clk_sel_mask = BIT_U16(3), .mac_speed_mask = BIT_U16(7), + + .supports_rmii = true, }; #define RK3368_GRF_SOC_CON15 0x043c @@ -569,13 +550,8 @@ static void rk3368_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3368_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3368_ops = { .set_to_rgmii = rk3368_set_to_rgmii, - .set_to_rmii = rk3368_set_to_rmii, .phy_intf_sel_grf_reg = RK3368_GRF_SOC_CON15, .phy_intf_sel_mask = GENMASK_U16(11, 9), @@ -585,6 +561,8 @@ static const struct rk_gmac_ops rk3368_ops = { .gmii_clk_sel_mask = GENMASK_U16(5, 4), .rmii_clk_sel_mask = BIT_U16(3), .mac_speed_mask = BIT_U16(7), + + .supports_rmii = true, }; #define RK3399_GRF_SOC_CON5 0xc214 @@ -611,13 +589,8 @@ static void rk3399_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3399_GMAC_CLK_TX_DL_CFG(tx_delay)); } -static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3399_ops = { .set_to_rgmii = rk3399_set_to_rgmii, - .set_to_rmii = rk3399_set_to_rmii, .phy_intf_sel_grf_reg = RK3399_GRF_SOC_CON5, .phy_intf_sel_mask = GENMASK_U16(11, 9), @@ -627,6 +600,8 @@ static const struct rk_gmac_ops rk3399_ops = { .gmii_clk_sel_mask = GENMASK_U16(5, 4), .rmii_clk_sel_mask = BIT_U16(3), .mac_speed_mask = BIT_U16(7), + + .supports_rmii = true, }; #define RK3506_GRF_SOC_CON8 0x0020 @@ -858,18 +833,15 @@ static void rk3568_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3568_GMAC_TXCLK_DLY_ENABLE); } -static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rk3568_ops = { .init = rk3568_init, .set_to_rgmii = rk3568_set_to_rgmii, - .set_to_rmii = rk3568_set_to_rmii, .set_speed = rk_set_clk_mac_speed, .phy_intf_sel_mask = GENMASK_U16(6, 4), + .supports_rmii = true, + .regs_valid = true, .regs = { 0xfe2a0000, /* gmac0 */ @@ -943,10 +915,6 @@ static void rk3576_set_to_rgmii(struct rk_priv_data *bsp_priv, RK3576_GMAC_CLK_RX_DL_CFG(rx_delay)); } -static void rk3576_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input, bool enable) { @@ -966,7 +934,6 @@ static void rk3576_set_clock_selection(struct rk_priv_data *bsp_priv, bool input static const struct rk_gmac_ops rk3576_ops = { .init = rk3576_init, .set_to_rgmii = rk3576_set_to_rgmii, - .set_to_rmii = rk3576_set_to_rmii, .set_clock_selection = rk3576_set_clock_selection, .rmii_mode_mask = BIT_U16(3), @@ -974,6 +941,8 @@ static const struct rk_gmac_ops rk3576_ops = { .gmii_clk_sel_mask = GENMASK_U16(6, 5), .rmii_clk_sel_mask = BIT_U16(5), + .supports_rmii = true, + .php_grf_required = true, .regs_valid = true, .regs = { @@ -1093,19 +1062,15 @@ static const struct rk_gmac_ops rk3588_ops = { #define RV1108_GMAC_FLOW_CTRL GRF_BIT(3) #define RV1108_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(3) -static void rv1108_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rv1108_ops = { - .set_to_rmii = rv1108_set_to_rmii, - .phy_intf_sel_grf_reg = RV1108_GRF_GMAC_CON0, .phy_intf_sel_mask = GENMASK_U16(6, 4), .speed_grf_reg = RV1108_GRF_GMAC_CON0, .rmii_clk_sel_mask = BIT_U16(7), .mac_speed_mask = BIT_U16(2), + + .supports_rmii = true, }; #define RV1126_GRF_GMAC_CON0 0X0070 @@ -1149,17 +1114,14 @@ static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv, RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay)); } -static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv) -{ -} - static const struct rk_gmac_ops rv1126_ops = { .set_to_rgmii = rv1126_set_to_rgmii, - .set_to_rmii = rv1126_set_to_rmii, .set_speed = rk_set_clk_mac_speed, .phy_intf_sel_grf_reg = RV1126_GRF_GMAC_CON0, .phy_intf_sel_mask = GENMASK_U16(6, 4), + + .supports_rmii = true, }; static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) -- 2.47.3