Add description for the Svrsw60t59b extension (PTE Reserved for SW bits 60:59) extension which was ratified recently in riscv-non-isa/riscv-iommu. Signed-off-by: Chunyan Zhang --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..7e1a59c7d911 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -217,6 +217,12 @@ properties: memory types as ratified in the 20191213 version of the privileged ISA specification. + - const: svrsw60t59b + description: + The svrsw60t59b for providing two more bits[60:59] to PTE/PMD entry + as ratified at commit 28bde925e7a7 ("PTE Reserved for SW bits 60:59") + of riscv-non-isa/riscv-iommu. + - const: svvptc description: The standard Svvptc supervisor-level extension for -- 2.34.1