Implement feature detection and sanitization for arm64 KVM guests on s390. Query hardware capabilities using QAAF instruction and sanitize arm64 ID registers. Provide accessor functions for queried capabilities and integrate feature detection into module initialization sequence. Co-developed-by: Andreas Grapentin Signed-off-by: Andreas Grapentin Signed-off-by: Steffen Eiden --- arch/s390/include/asm/kvm_host_arm64.h | 13 +++ arch/s390/kvm/arm64/Makefile | 1 + arch/s390/kvm/arm64/arm.c | 2 +- arch/s390/kvm/arm64/feature.c | 163 +++++++++++++++++++++++++++++++++ arch/s390/kvm/arm64/feature.h | 86 +++++++++++++++++ arch/s390/kvm/arm64/qaaf.c | 2 + 6 files changed, 266 insertions(+), 1 deletion(-) diff --git a/arch/s390/include/asm/kvm_host_arm64.h b/arch/s390/include/asm/kvm_host_arm64.h index 3e69724f17c9..9afe37f6696c 100644 --- a/arch/s390/include/asm/kvm_host_arm64.h +++ b/arch/s390/include/asm/kvm_host_arm64.h @@ -15,6 +15,19 @@ enum vcpu_sysreg; #include +enum { + ARM64_HAS_WFXT, + ARM64_HAS_RASV1P1_EXTN, + ARM64_HAS_STAGE2_FWB, + ARM64_HAS_RAS_EXTN, + ARM64_HAS_EVT, + ARM64_HAS_HCR_NV1, + ARM64_MISMATCHED_CACHE_TYPE, + ARM64_HAS_ECV_CNTPOFF, +}; + +bool cpus_have_final_cap(unsigned int num); + #define KVM_HAVE_MMU_RWLOCK #define KVM_MAX_VCPUS 1 #define __KVM_HAVE_VCPU_RUN_PID_CHANGE diff --git a/arch/s390/kvm/arm64/Makefile b/arch/s390/kvm/arm64/Makefile index e9587c6d6de9..e75b38071f8a 100644 --- a/arch/s390/kvm/arm64/Makefile +++ b/arch/s390/kvm/arm64/Makefile @@ -11,6 +11,7 @@ ccflags-y += -I $(src) -I $(objtree)/$(obj) -I$(srctree)/arch/$(SRCARCH)/kvm/gma kvm-arm64-local := \ arm.o \ + feature.o \ guest.o \ handle_exit.o \ inject_fault.o \ diff --git a/arch/s390/kvm/arm64/arm.c b/arch/s390/kvm/arm64/arm.c index 3af0b47b8377..ba6235629c7d 100644 --- a/arch/s390/kvm/arm64/arm.c +++ b/arch/s390/kvm/arm64/arm.c @@ -20,6 +20,7 @@ #include #include "arm.h" +#include "feature.h" #include "handle_exit.h" #include "qaaf.h" @@ -27,7 +28,6 @@ #include "trace.h" static unsigned long system_supported_vcpu_features(struct kvm_vcpu *vcpu); -#define read_sanitised_ftr_reg(_id) 0 #define __INCL_GEN_ARM_FILE #include "generated/arm.inc" diff --git a/arch/s390/kvm/arm64/feature.c b/arch/s390/kvm/arm64/feature.c new file mode 100644 index 000000000000..f8b23ba85f9e --- /dev/null +++ b/arch/s390/kvm/arm64/feature.c @@ -0,0 +1,163 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#include +#include +#include +#include + +#include + +#include "feature.h" + +#define MASK_RESERVED(_qaafp, _id) \ + ({ \ + u64 *_reg = &((_qaafp)->regs[QAAF_REG_##_id]); \ + *_reg = (*_reg & ~_id##_RES0) | _id##_RES1; \ + }) + +#define QAAF_FIELD_MODIFY(_idp, _id_field, _val) \ + FIELD_MODIFY(_id_field##_MASK, _idp, _id_field##_##_val) + +#define MODIFY(_qaafp, _id, _field, _val) \ + QAAF_FIELD_MODIFY(&((_qaafp)->regs[QAAF_REG_##_id]), _id##_##_field, _val) + +void __init kvm_arm_host_sanitize_features(struct qaaf_qmc_block *qaaf_qmc) +{ + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR0_EL1); + + MODIFY(qaaf_qmc, ID_AA64ISAR1_EL1, LS64, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR1_EL1); + + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, SYSINSTR_128, NI); + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, SYSREG_128, NI); + MODIFY(qaaf_qmc, ID_AA64ISAR2_EL1, PAC_frac, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64ISAR3_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR2_EL1); + + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, Spec_FPACC, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, ADERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, SDERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, ANERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, SNERR, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR3_EL1, MEC, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR3_EL1); + + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, SRMASK, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, E3DSE, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, RMEGDI, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, FGWTE3, NI); + MODIFY(qaaf_qmc, ID_AA64MMFR4_EL1, ASID2, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64MMFR4_EL1); + + MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SEL2, NI); + MODIFY(qaaf_qmc, ID_AA64PFR0_EL1, SVE, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64PFR2_EL1); + + MODIFY(qaaf_qmc, ID_AA64DFR0_EL1, PMUVer, NI); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64DFR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64AFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_AA64AFR1_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64ZFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64SMFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_AA64FPFR0_EL1); + + MASK_RESERVED(qaaf_qmc, ID_PFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_PFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_PFR2_EL1); + + MASK_RESERVED(qaaf_qmc, ID_DFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_DFR1_EL1); + + MASK_RESERVED(qaaf_qmc, ID_MMFR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR2_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR3_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR4_EL1); + MASK_RESERVED(qaaf_qmc, ID_MMFR5_EL1); + + MASK_RESERVED(qaaf_qmc, ID_ISAR0_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR1_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR2_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR3_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR4_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR5_EL1); + MASK_RESERVED(qaaf_qmc, ID_ISAR6_EL1); + + MASK_RESERVED(qaaf_qmc, MVFR0_EL1); + MASK_RESERVED(qaaf_qmc, MVFR1_EL1); + MASK_RESERVED(qaaf_qmc, MVFR2_EL1); + + MASK_RESERVED(qaaf_qmc, CTR_EL0); + + MASK_RESERVED(qaaf_qmc, ICH_VTR_EL2); +} + +/** + * cpus_have_final_cap - Check if an ARM64 CPU capability is supported + * @num: Capability number to check + * + * Maps ARM64 CPU capabilities to their corresponding ID register fields + * and checks if the feature is supported by the s390 hardware via QAAF. + * + * Return: true if capability is supported, false otherwise + */ +bool cpus_have_final_cap(unsigned int num) +{ + u64 reg_val; + + switch (num) { + case ARM64_HAS_STAGE2_FWB: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + return SYS_FIELD_GET(ID_AA64MMFR2_EL1, FWB, reg_val) >= + ID_AA64MMFR2_EL1_FWB_IMP; + + case ARM64_HAS_WFXT: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); + return SYS_FIELD_GET(ID_AA64ISAR2_EL1, WFxT, reg_val) >= + ID_AA64ISAR2_EL1_WFxT_IMP; + + case ARM64_HAS_RASV1P1_EXTN: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); + return SYS_FIELD_GET(ID_AA64PFR1_EL1, RAS_frac, reg_val) == + ID_AA64PFR1_EL1_RAS_frac_RASv1p1; + + case ARM64_HAS_HCR_NV1: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR4_EL1); + return SYS_FIELD_GET(ID_AA64MMFR4_EL1, E2H0, reg_val) == + ID_AA64MMFR4_EL1_E2H0_IMP; + + case ARM64_HAS_RAS_EXTN: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + return SYS_FIELD_GET(ID_AA64PFR0_EL1, RAS, reg_val) >= + ID_AA64PFR0_EL1_RAS_IMP; + + case ARM64_HAS_EVT: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR2_EL1); + return SYS_FIELD_GET(ID_AA64MMFR2_EL1, EVT, reg_val) >= + ID_AA64MMFR2_EL1_EVT_IMP; + + case ARM64_HAS_ECV_CNTPOFF: + reg_val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); + return SYS_FIELD_GET(ID_AA64MMFR0_EL1, ECV, reg_val) >= + ID_AA64MMFR0_EL1_ECV_CNTPOFF; + + case ARM64_MISMATCHED_CACHE_TYPE: + return false; + default: + return false; + } +} diff --git a/arch/s390/kvm/arm64/feature.h b/arch/s390/kvm/arm64/feature.h new file mode 100644 index 000000000000..0a59047fda6e --- /dev/null +++ b/arch/s390/kvm/arm64/feature.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef ARCH_S390_KVM_FEATURE_H +#define ARCH_S390_KVM_FEATURE_H + +#include +#include + +#include + +#include "qaaf.h" + +void __init kvm_arm_host_sanitize_features(struct qaaf_qmc_block *qaaf_qmc); + +/** + * read_sanitised_ftr_reg() - Get the value of a sys register + * + * @id - ARM sysreg id + * + * Get the value of a sys register describing the host configuration. + * The returned value indicates support by the machine (HW/FW) + * after some sanitisation. + * + * Example: + * read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1) + * + * Return: Sanitised HW value of the specified register + */ +static inline u64 read_sanitised_ftr_reg(u32 id) +{ + return kvm_qaaf_read_ftr_reg(id); +} + +/** + * kvm_sae_supported_sd_formats() - Retrieve supported SAE SD formats + * + * Return: Bitmap of supported SAE state description formats. + */ +static inline u32 kvm_sae_supported_sd_formats(void) +{ + struct qaaf_qmc_block *qmc = kvm_qaaf_qmc(); + + return qmc->ssdf; +} + +/** + * kvm_sae_supported_sa_formats() - Retrieve supported SAE SA formats + * + * Return: Bitmap of supported SAE save area formats. + */ +static inline u32 kvm_sae_supported_sa_formats(void) +{ + struct qaaf_qmc_block *qmc = kvm_qaaf_qmc(); + + return qmc->ssaf; +} + +/** + * kvm_sae_max_vcpus() - Retrieve maximum supported vcpus + * + * Return: Max number of vCPUs supported by the SAE instruction/the machine + * as indicated by QAAF, not necessarily that supported by the host software. + */ +static inline u32 kvm_sae_max_vcpus(void) +{ + struct qaaf_qmc_block *qmc = kvm_qaaf_qmc(); + + /* QAAF QMC reports the max id not the max num */ + return qmc->maxncpu + 1; +} + +/** + * kvm_sae_irptc() - Retrieve supported SAE IRPTCs + * + * Return: Bitmap of supported SAE IRPTCs. + */ +static inline u64 kvm_sae_irptc(void) +{ + struct qaaf_qmc_block *qmc = kvm_qaaf_qmc(); + + return qmc->regs[QAAF_IRPTC]; +} + +#define kvm_vcpu_has_pmu(_v) false + +#endif /* ARCH_S390_KVM_FEATURE_H */ diff --git a/arch/s390/kvm/arm64/qaaf.c b/arch/s390/kvm/arm64/qaaf.c index f6b1750aed68..36487025013c 100644 --- a/arch/s390/kvm/arm64/qaaf.c +++ b/arch/s390/kvm/arm64/qaaf.c @@ -3,6 +3,7 @@ #include #include #include "qaaf.h" +#include "feature.h" static struct qaaf_qmc_block qmc_sanitized; @@ -17,6 +18,7 @@ struct qaaf_qmc_block *kvm_qaaf_qmc(void) void __init kvm_init_qaaf(void) { qmc_sanitized = *aef_qmc(); + kvm_arm_host_sanitize_features(&qmc_sanitized); } #define _qaaf_reg_case(id) case SYS_##id: return qmc_sanitized.regs[QAAF_REG_##id] -- 2.56.0