A data race on APICCommonState->apicbase was detected by ThreadSanitizer. To resolve this race, direct accesses to s->apicbase are converted to use the appropriate qatomic_*__nocheck() atomic operations. This ensures that reads and writes are properly ordered and visible across threads. This patch depends on the previous commit changing the type of `apicbase` to `uint64_t`. The race was identified by the following TSAN report: ================== WARNING: ThreadSanitizer: data race Read of size 8 at ... by main thread: #0 cpu_is_apic_enabled hw/intc/apic_common.c:75:15 ... #15 main_loop_wait util/main-loop.c:600:5 ... Previous write of size 8 at ... by thread T7 'CPU 0/KVM': #0 kvm_apic_set_base hw/i386/kvm/apic.c:101:17 #1 cpu_set_apic_base hw/intc/apic_common.c:47:16 #2 kvm_arch_post_run target/i386/kvm/kvm.c:5621:5 #3 kvm_cpu_exec accel/kvm/kvm-all.c:3229:17 #4 kvm_vcpu_thread_fn accel/kvm/kvm-accel-ops.c:51:17 ... SUMMARY: ThreadSanitizer: data race hw/intc/apic_common.c:75:15 in cpu_is_apic_enabled ================== Signed-off-by: Marc Morcos --- hw/i386/kvm/apic.c | 12 ++++++++---- hw/intc/apic_common.c | 20 ++++++++++++-------- 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 82355f0463..b9b03c529f 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -34,9 +34,10 @@ static inline uint32_t kvm_apic_get_reg(struct kvm_lapic_state *kapic, static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) { int i; + uint64_t apicbase = qatomic_read__nocheck(&s->apicbase); memset(kapic, 0, sizeof(*kapic)); - if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { + if (kvm_has_x2apic_api() && apicbase & MSR_IA32_APICBASE_EXTD) { kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id); } else { kvm_apic_set_reg(kapic, 0x2, s->id << 24); @@ -63,8 +64,9 @@ static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) { int i, v; + uint64_t apicbase = qatomic_read__nocheck(&s->apicbase); - if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { + if (kvm_has_x2apic_api() && apicbase & MSR_IA32_APICBASE_EXTD) { assert(kvm_apic_get_reg(kapic, 0x2) == s->initial_apic_id); } else { s->id = kvm_apic_get_reg(kapic, 0x2) >> 24; @@ -97,7 +99,7 @@ void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) static int kvm_apic_set_base(APICCommonState *s, uint64_t val) { - s->apicbase = val; + qatomic_set__nocheck(&s->apicbase, val); return 0; } @@ -140,12 +142,14 @@ static void kvm_apic_put(CPUState *cs, run_on_cpu_data data) APICCommonState *s = data.host_ptr; struct kvm_lapic_state kapic; int ret; + uint64_t apicbase; if (is_tdx_vm()) { return; } - kvm_put_apicbase(s->cpu, s->apicbase); + apicbase = qatomic_read__nocheck(&s->apicbase); + kvm_put_apicbase(s->cpu, apicbase); kvm_put_apic_state(s, &kapic); ret = kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 1e9aba2e48..9e42189d8a 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -19,6 +19,7 @@ */ #include "qemu/osdep.h" +#include "qemu/atomic.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" @@ -52,8 +53,9 @@ int cpu_set_apic_base(APICCommonState *s, uint64_t val) uint64_t cpu_get_apic_base(APICCommonState *s) { if (s) { - trace_cpu_get_apic_base((uint64_t)s->apicbase); - return s->apicbase; + uint64_t apicbase = qatomic_read__nocheck(&s->apicbase); + trace_cpu_get_apic_base(apicbase); + return apicbase; } else { trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); return MSR_IA32_APICBASE_BSP; @@ -66,7 +68,7 @@ bool cpu_is_apic_enabled(APICCommonState *s) return false; } - return s->apicbase & MSR_IA32_APICBASE_ENABLE; + return qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_ENABLE; } void cpu_set_apic_tpr(APICCommonState *s, uint8_t val) @@ -223,9 +225,9 @@ void apic_designate_bsp(APICCommonState *s, bool bsp) } if (bsp) { - s->apicbase |= MSR_IA32_APICBASE_BSP; + qatomic_fetch_or(&s->apicbase, MSR_IA32_APICBASE_BSP); } else { - s->apicbase &= ~MSR_IA32_APICBASE_BSP; + qatomic_fetch_and(&s->apicbase, ~MSR_IA32_APICBASE_BSP); } } @@ -235,8 +237,9 @@ static void apic_reset_common(DeviceState *dev) APICCommonClass *info = APIC_COMMON_GET_CLASS(s); uint64_t bsp; - bsp = s->apicbase & MSR_IA32_APICBASE_BSP; - s->apicbase = APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; + bsp = qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_BSP; + qatomic_set__nocheck(&s->apicbase, + APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE); s->id = s->initial_apic_id; kvm_reset_irq_delivered(); @@ -405,7 +408,8 @@ static void apic_common_get_id(Object *obj, Visitor *v, const char *name, APICCommonState *s = APIC_COMMON(obj); uint32_t value; - value = s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : s->id; + value = qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_EXTD ? + s->initial_apic_id : s->id; visit_type_uint32(v, name, &value, errp); } -- 2.52.0.239.gd5f0c6e74e-goog