From: "Jan Petrous (OSS)" Add the two PCIe controllers of the S32G2 and S32G3, disabled. Each is the root complex half of one SerDes subsystem: PCIe_0 pairs with SerDes_0 and PCIe_1 with SerDes_1. A board device tree that routes a SerDes lane to PCIe enables the controller and points the root port at the lane PHY child node of the matching SerDes. Both SoCs integrate the controllers identically - same register layout and same GIC SPI assignment - so the nodes differ only in the compatible: S32G3 adds "nxp,s32g3-pcie" ahead of the "nxp,s32g2-pcie" base, as the binding describes. The S32G3-VNP-RDB3 and the S32G2-VNP-RDB2 wire the same two root complexes to the M.2 slots and the PCIe card slot. Their configuration space (0x5f_ffffe000 and 0x4f_ffffe000) lies above the 32-bit window mapped by soc@0, so the controllers are described at the device tree root rather than under soc@0. The root ports are labelled (pcie0_rp, pcie1_rp) so board device trees can extend them by label. An overlay that instead re-declares a pcie@0 child inside the controller node makes dtc emit a unit_address_vs_reg warning, because the overlay alone carries no reg for that node. The GIC nodes gain '#address-cells = <0>'. The PCIe interrupt-map entries name the GIC as their interrupt parent, and without it dtc warns on every entry and falls back to zero. Only the S32G3-VNP-RDB3 board device trees in this series enable a controller; the S32G2 nodes stay disabled until a board enables them. Signed-off-by: Jan Petrous (OSS) --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 81 ++++++++++++++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 81 ++++++++++++++++++++++++++++++++ 2 files changed, 162 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 404913b208fb..539840340318 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -918,7 +918,88 @@ gic: interrupt-controller@50800000 { <0x50420000 0x2000>; interrupts = ; interrupt-controller; + #address-cells = <0>; #interrupt-cells = <3>; }; }; + + /* + * PCIe controllers. Their config space (0x5f_ffffe000 / 0x4f_ffffe000) + * lies above the 32-bit window mapped by soc@0, so the root complexes + * are described at the device tree root. Disabled here; a board file + * that wires a lane to PCIe enables the controller and adds the phys. + */ + pcie0: pcie@40400000 { + compatible = "nxp,s32g2-pcie"; + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 */ + <0x00 0x40460000 0x0 0x00001000>, /* atu */ + <0x00 0x40470000 0x0 0x00001000>, /* dma */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl */ + <0x5f 0xffffe000 0x0 0x00002000>; /* config */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>, + <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>, + <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>; + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + pcie0_rp: pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + }; + }; + + pcie1: pcie@44100000 { + compatible = "nxp,s32g2-pcie"; + reg = <0x00 0x44100000 0x0 0x00001000>, /* dbi */ + <0x00 0x44120000 0x0 0x00001000>, /* dbi2 */ + <0x00 0x44160000 0x0 0x00001000>, /* atu */ + <0x00 0x44170000 0x0 0x00001000>, /* dma */ + <0x00 0x44181000 0x0 0x000000f8>, /* ctrl */ + <0x4f 0xffffe000 0x0 0x00002000>; /* config */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x01000000 0x0 0x00000000 0x4f 0xfffe0000 0x0 0x00010000>, + <0x02000000 0x0 0x00000000 0x48 0x00000000 0x0 0x80000000>, + <0x02000000 0x1 0x00000000 0x49 0x00000000 0x6 0xfffe0000>; + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + pcie1_rp: pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + }; + }; }; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 0d001b2895c6..fdf086363c02 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -1058,6 +1058,7 @@ stm11: timer@4052c000 { gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; + #address-cells = <0>; #interrupt-cells = <3>; interrupt-controller; reg = <0x50800000 0x10000>, @@ -1069,6 +1070,86 @@ gic: interrupt-controller@50800000 { }; }; + /* + * PCIe controllers. Their config space (0x5f_ffffe000 / 0x4f_ffffe000) + * lies above the 32-bit window mapped by soc@0, so the root complexes + * are described at the device tree root. Disabled here; a board file + * that wires a lane to PCIe enables the controller and adds the phys. + */ + pcie0: pcie@40400000 { + compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie"; + reg = <0x00 0x40400000 0x0 0x00001000>, /* dbi */ + <0x00 0x40420000 0x0 0x00001000>, /* dbi2 */ + <0x00 0x40460000 0x0 0x00001000>, /* atu */ + <0x00 0x40470000 0x0 0x00001000>, /* dma */ + <0x00 0x40481000 0x0 0x000000f8>, /* ctrl */ + <0x5f 0xffffe000 0x0 0x00002000>; /* config */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x01000000 0x0 0x00000000 0x5f 0xfffe0000 0x0 0x00010000>, + <0x02000000 0x0 0x00000000 0x58 0x00000000 0x0 0x80000000>, + <0x02000000 0x1 0x00000000 0x59 0x00000000 0x6 0xfffe0000>; + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + pcie0_rp: pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + }; + }; + + pcie1: pcie@44100000 { + compatible = "nxp,s32g3-pcie", "nxp,s32g2-pcie"; + reg = <0x00 0x44100000 0x0 0x00001000>, /* dbi */ + <0x00 0x44120000 0x0 0x00001000>, /* dbi2 */ + <0x00 0x44160000 0x0 0x00001000>, /* atu */ + <0x00 0x44170000 0x0 0x00001000>, /* dma */ + <0x00 0x44181000 0x0 0x000000f8>, /* ctrl */ + <0x4f 0xffffe000 0x0 0x00002000>; /* config */ + reg-names = "dbi", "dbi2", "atu", "dma", "ctrl", "config"; + dma-coherent; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x01000000 0x0 0x00000000 0x4f 0xfffe0000 0x0 0x00010000>, + <0x02000000 0x0 0x00000000 0x48 0x00000000 0x0 0x80000000>, + <0x02000000 0x1 0x00000000 0x49 0x00000000 0x6 0xfffe0000>; + bus-range = <0x0 0xff>; + interrupts = , + ; + interrupt-names = "msi", "dma"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + pcie1_rp: pcie@0 { + reg = <0x0 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + }; + }; + timer { compatible = "arm,armv8-timer"; interrupt-parent = <&gic>; -- 2.55.0