From: Dapeng Mi If IA32_PERF_CAPABILITIES.FW_WRITE (bit 13) is set, each general- purpose counter IA32_PMCi (starting at 0xc1) is accompanied by a corresponding 64-bit alias MSR starting at 0x4c1 (IA32_A_PMC0). The legacy IA32_PMCi MSRs are not full-width and their effective width is determined by CPUID.0AH:EAX[23:16]. Since these MSRs are architectural aliases, when IA32_A_PMCi is supported it is safe to use it for save/restore instead of the legacy IA32_PMCi MSRs. Full-width write is a user-visible feature and can be disabled individually. Signed-off-by: Dapeng Mi Signed-off-by: Zide Chen --- V3: - Move the MAX_GP_COUNTERS change and migrate version ID code to [patch v3 4/13] to avoid bumping version IDs twice in one patch series. V2: - Slightly improve the commit message wording. - Update the comment for MSR_IA32_PMC0 definition. --- target/i386/cpu.h | 3 +++ target/i386/kvm/kvm.c | 18 ++++++++++++++++-- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5288c92fe52f..8cc3c2f139e7 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -421,6 +421,7 @@ typedef enum X86Seg { #define MSR_IA32_PERF_CAPABILITIES 0x345 #define PERF_CAP_LBR_FMT 0x3f +#define PERF_CAP_FULL_WRITE (1U << 13) #define MSR_IA32_TSX_CTRL 0x122 #define MSR_IA32_TSCDEADLINE 0x6e0 @@ -448,6 +449,8 @@ typedef enum X86Seg { #define MSR_IA32_SGXLEPUBKEYHASH3 0x8f #define MSR_P6_PERFCTR0 0xc1 +/* Alias MSR range for full-width general-purpose performance counters */ +#define MSR_IA32_PMC0 0x4c1 #define MSR_IA32_SMBASE 0x9e #define MSR_SMI_COUNT 0x34 diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 5c953a0f3a60..a99c1dba83f2 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4270,6 +4270,12 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) } if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0) { + uint32_t perf_cntr_base = MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRITE) { + perf_cntr_base = MSR_IA32_PMC0; + } + if (pmu_version > 1) { /* Stop the counter. */ kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); @@ -4282,7 +4288,7 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level) env->msr_fixed_counters[i]); } for (i = 0; i < num_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, + kvm_msr_entry_add(cpu, perf_cntr_base + i, env->msr_gp_counters[i]); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, env->msr_gp_evtsel[i]); @@ -4844,6 +4850,11 @@ static int kvm_get_msrs(X86CPU *cpu) } if ((IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env)) && pmu_version > 0) { + uint32_t perf_cntr_base = MSR_P6_PERFCTR0; + + if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_FULL_WRITE) { + perf_cntr_base = MSR_IA32_PMC0; + } if (pmu_version > 1) { kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0); kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0); @@ -4853,7 +4864,7 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0); } for (i = 0; i < num_pmu_gp_counters; i++) { - kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); + kvm_msr_entry_add(cpu, perf_cntr_base + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } } @@ -5218,6 +5229,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1: env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data; break; + case MSR_IA32_PMC0 ... MSR_IA32_PMC0 + MAX_GP_COUNTERS - 1: + env->msr_gp_counters[index - MSR_IA32_PMC0] = msrs[i].data; + break; case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data; break; -- 2.54.0