From: Zhi Li Enable the on-board Gigabit Ethernet controller on the HiFive Premier P550 development board. Signed-off-by: Zhi Li --- .../dts/eswin/eic7700-hifive-premier-p550.dts | 50 +++++++++++++++++ arch/riscv/boot/dts/eswin/eic7700.dtsi | 54 +++++++++++++++++++ 2 files changed, 104 insertions(+) diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts index 131ed1fc6b2e..d558f0fdfb38 100644 --- a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts +++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts @@ -13,6 +13,8 @@ / { aliases { serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; }; chosen { @@ -20,6 +22,54 @@ chosen { }; }; +&gmac0 { + phy-handle = <&gmac0_phy0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio106_pins>; + rx-internal-delay-ps = <20>; + tx-internal-delay-ps = <100>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + gmac0_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-gpios = <&gpioD 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + +&gmac1 { + phy-handle = <&gmac1_phy0>; + phy-mode = "rgmii-rxid"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio111_pins>; + rx-internal-delay-ps = <200>; + tx-internal-delay-ps = <200>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + gmac1_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-gpios = <&gpioD 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi index c3ed93008bca..c6f504f0d096 100644 --- a/arch/riscv/boot/dts/eswin/eic7700.dtsi +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi @@ -5,6 +5,8 @@ /dts-v1/; +#include + / { #address-cells = <2>; #size-cells = <2>; @@ -295,6 +297,58 @@ uart4: serial@50940000 { status = "disabled"; }; + gmac0: ethernet@50400000 { + compatible = "eswin,eic7700-qos-eth", "snps,dwmac-5.20"; + reg = <0x0 0x50400000 0x0 0x10000>; + interrupts = <61>; + interrupt-names = "macirq"; + clocks = <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 193>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 95>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x100 0x108 0x114 0x118 0x11c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac0>; + status = "disabled"; + + stmmac_axi_setup_gmac0: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; + + gmac1: ethernet@50410000 { + compatible = "eswin,eic7700-qos-eth-clk-inversion", "snps,dwmac-5.20"; + reg = <0x0 0x50410000 0x0 0x10000>; + interrupts = <70>; + interrupt-names = "macirq"; + clocks = <&clk 186>, + <&clk 171>, + <&clk 40>, + <&clk 194>; + clock-names = "axi", "cfg", "stmmaceth", "tx"; + resets = <&reset 94>; + reset-names = "stmmaceth"; + eswin,hsp-sp-csr = <&hsp_sp_csr 0x200 0x208 0x214 0x218 0x21c>; + snps,aal; + snps,fixed-burst; + snps,tso; + snps,axi-config = <&stmmac_axi_setup_gmac1>; + status = "disabled"; + + stmmac_axi_setup_gmac1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <2>; + snps,wr_osr_lmt = <2>; + }; + }; + gpio@51600000 { compatible = "snps,dw-apb-gpio"; reg = <0x0 0x51600000 0x0 0x80>; -- 2.25.1