From: Irving-CH Lin Add support for the MT8189 dispsys clock controller, which provides clock gate control for display system. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 12 ++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-dispsys.c | 172 ++++++++++++++++++++++ 3 files changed, 185 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-dispsys.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 316d010b503a..8b1f358457d8 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -917,6 +917,18 @@ config COMMON_CLK_MT8189_MFG the MT8189 chipset. Enabling this will allow the manufacturing mode of the chipset to function correctly with the appropriate clock settings. +config COMMON_CLK_MT8189_MMSYS + tristate "Clock driver for MediaTek MT8189 mmsys" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + Enable this to support the clock framework for MediaTek MT8189 + multimedia systems (mmsys). This driver is responsible for managing + the clocks for various multimedia components within the SoC, such as + video, audio, and image processing units. Enabling this option will + ensure that these components receive the correct clock frequencies + for proper operation. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 07f11760cf68..21a9e6264b84 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -133,6 +133,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o obj-$(CONFIG_COMMON_CLK_MT8189_IMG) += clk-mt8189-img.o obj-$(CONFIG_COMMON_CLK_MT8189_MDPSYS) += clk-mt8189-mdpsys.o obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o +obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) += clk-mt8189-dispsys.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-dispsys.c b/drivers/clk/mediatek/clk-mt8189-dispsys.c new file mode 100644 index 000000000000..4c101cf66f91 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-dispsys.c @@ -0,0 +1,172 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs mm0_cg_regs = { + .set_ofs = 0x04, + .clr_ofs = 0x08, + .sta_ofs = 0x00, +}; + +static const struct mtk_gate_regs mm1_cg_regs = { + .set_ofs = 0x14, + .clr_ofs = 0x18, + .sta_ofs = 0x10, +}; + +#define GATE_MM0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_MM1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mm1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mm_clks[] = { + /* MM0 */ + GATE_MM0(CLK_MM_DISP_OVL0_4L, "mm_disp_ovl0_4l", "disp0_sel", 0), + GATE_MM0(CLK_MM_DISP_OVL1_4L, "mm_disp_ovl1_4l", "disp0_sel", 1), + GATE_MM0(CLK_MM_VPP_RSZ0, "mm_vpp_rsz0", "disp0_sel", 2), + GATE_MM0(CLK_MM_VPP_RSZ1, "mm_vpp_rsz1", "disp0_sel", 3), + GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "disp0_sel", 4), + GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "disp0_sel", 5), + GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "disp0_sel", 6), + GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "disp0_sel", 7), + GATE_MM0(CLK_MM_DISP_CCORR0, "mm_disp_ccorr0", "disp0_sel", 8), + GATE_MM0(CLK_MM_DISP_CCORR1, "mm_disp_ccorr1", "disp0_sel", 9), + GATE_MM0(CLK_MM_DISP_CCORR2, "mm_disp_ccorr2", "disp0_sel", 10), + GATE_MM0(CLK_MM_DISP_CCORR3, "mm_disp_ccorr3", "disp0_sel", 11), + GATE_MM0(CLK_MM_DISP_AAL0, "mm_disp_aal0", "disp0_sel", 12), + GATE_MM0(CLK_MM_DISP_AAL1, "mm_disp_aal1", "disp0_sel", 13), + GATE_MM0(CLK_MM_DISP_GAMMA0, "mm_disp_gamma0", "disp0_sel", 14), + GATE_MM0(CLK_MM_DISP_GAMMA1, "mm_disp_gamma1", "disp0_sel", 15), + GATE_MM0(CLK_MM_DISP_DITHER0, "mm_disp_dither0", "disp0_sel", 16), + GATE_MM0(CLK_MM_DISP_DITHER1, "mm_disp_dither1", "disp0_sel", 17), + GATE_MM0(CLK_MM_DISP_DSC_WRAP0, "mm_disp_dsc_wrap0", "disp0_sel", 18), + GATE_MM0(CLK_MM_VPP_MERGE0, "mm_vpp_merge0", "disp0_sel", 19), + GATE_MM0(CLK_MMSYS_0_DISP_DVO, "mmsys_0_disp_dvo", "disp0_sel", 20), + GATE_MM0(CLK_MMSYS_0_DISP_DSI0, "mmsys_0_CLK0", "disp0_sel", 21), + GATE_MM0(CLK_MM_DP_INTF0, "mm_dp_intf0", "disp0_sel", 22), + GATE_MM0(CLK_MM_DPI0, "mm_dpi0", "disp0_sel", 23), + GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "disp0_sel", 24), + GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "disp0_sel", 25), + GATE_MM0(CLK_MM_DISP_FAKE_ENG0, "mm_disp_fake_eng0", "disp0_sel", 26), + GATE_MM0(CLK_MM_DISP_FAKE_ENG1, "mm_disp_fake_eng1", "disp0_sel", 27), + GATE_MM0(CLK_MM_SMI_LARB, "mm_smi_larb", "disp0_sel", 28), + GATE_MM0(CLK_MM_DISP_MUTEX0, "mm_disp_mutex0", "disp0_sel", 29), + GATE_MM0(CLK_MM_DIPSYS_CONFIG, "mm_dipsys_config", "disp0_sel", 30), + GATE_MM0(CLK_MM_DUMMY, "mm_dummy", "disp0_sel", 31), + /* MM1 */ + GATE_MM1(CLK_MMSYS_1_DISP_DSI0, "mmsys_1_CLK0", "dsi_occ_sel", 0), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER, "mmsys_1_lvds_encoder", "pll_dpix_sel", 1), + GATE_MM1(CLK_MMSYS_1_DPI0, "mmsys_1_dpi0", "pll_dpix_sel", 2), + GATE_MM1(CLK_MMSYS_1_DISP_DVO, "mmsys_1_disp_dvo", "edp_sel", 3), + GATE_MM1(CLK_MM_DP_INTF, "mm_dp_intf", "dp_sel", 4), + GATE_MM1(CLK_MMSYS_1_LVDS_ENCODER_CTS, "mmsys_1_lvds_encoder_cts", "vdstx_dg_cts_sel", 5), + GATE_MM1(CLK_MMSYS_1_DISP_DVO_AVT, "mmsys_1_disp_dvo_avt", "edp_favt_sel", 6), +}; + +static const struct mtk_clk_desc mm_mcd = { + .clks = mm_clks, + .num_clks = ARRAY_SIZE(mm_clks), +}; + +static const struct mtk_gate_regs gce_d_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_GCE_D(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &gce_d_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate gce_d_clks[] = { + GATE_GCE_D(CLK_GCE_D_TOP, "gce_d_top", "mminfra_gce_d", 16), +}; + +static const struct mtk_clk_desc gce_d_mcd = { + .clks = gce_d_clks, + .num_clks = ARRAY_SIZE(gce_d_clks), +}; + +static const struct mtk_gate_regs gce_m_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x0, + .sta_ofs = 0x0, +}; + +#define GATE_GCE_M(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &gce_m_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr) + +static const struct mtk_gate gce_m_clks[] = { + GATE_GCE_M(CLK_GCE_M_TOP, "gce_m_top", "mminfra_gce_m", 16), +}; + +static const struct mtk_clk_desc gce_m_mcd = { + .clks = gce_m_clks, + .num_clks = ARRAY_SIZE(gce_m_clks), +}; + +static const struct mtk_gate_regs mminfra_config0_cg_regs = { + .set_ofs = 0x104, + .clr_ofs = 0x108, + .sta_ofs = 0x100, +}; + +static const struct mtk_gate_regs mminfra_config1_cg_regs = { + .set_ofs = 0x114, + .clr_ofs = 0x118, + .sta_ofs = 0x110, +}; + +#define GATE_MMINFRA_CONFIG0(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mminfra_config0_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +#define GATE_MMINFRA_CONFIG1(_id, _name, _parent, _shift) \ + GATE_MTK(_id, _name, _parent, &mminfra_config1_cg_regs, _shift, &mtk_clk_gate_ops_setclr) + +static const struct mtk_gate mminfra_config_clks[] = { + /* MMINFRA_CONFIG0 */ + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_D, "mminfra_gce_d", "mminfra_sel", 0), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_GCE_M, "mminfra_gce_m", "mminfra_sel", 1), + GATE_MMINFRA_CONFIG0(CLK_MMINFRA_SMI, "mminfra_smi", "mminfra_sel", 2), + /* MMINFRA_CONFIG1 */ + GATE_MMINFRA_CONFIG1(CLK_MMINFRA_GCE_26M, "mminfra_gce_26m", "mminfra_sel", 17), +}; + +static const struct mtk_clk_desc mminfra_config_mcd = { + .clks = mminfra_config_clks, + .num_clks = ARRAY_SIZE(mminfra_config_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_dispsys[] = { + { .compatible = "mediatek,mt8189-dispsys", .data = &mm_mcd }, + { .compatible = "mediatek,mt8189-gce-d", .data = &gce_d_mcd }, + { .compatible = "mediatek,mt8189-gce-m", .data = &gce_m_mcd }, + { .compatible = "mediatek,mt8189-mm-infra", .data = &mminfra_config_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dispsys); + +static struct platform_driver clk_mt8189_dispsys_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-dispsys", + .of_match_table = of_match_clk_mt8189_dispsys, + }, +}; + +module_platform_driver(clk_mt8189_dispsys_drv); +MODULE_DESCRIPTION("MediaTek MT8189 display clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2