From: Isaku Yamahata When APIC timer virtualization is enabled, the hardware handles the access to the guest TSC deadline MSR, not by the VMM. Disable/enable MSR intercept on TSC DEADLINE MSR based on the APIC timer virtualization bit of tertiary processor-based execution control. Signed-off-by: Isaku Yamahata --- arch/x86/kvm/vmx/nested.c | 22 ++++++++++++++++++++++ arch/x86/kvm/vmx/nested.h | 5 +++++ 2 files changed, 27 insertions(+) diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c index 3e02dee38e9c..191317479d5e 100644 --- a/arch/x86/kvm/vmx/nested.c +++ b/arch/x86/kvm/vmx/nested.c @@ -595,6 +595,26 @@ static inline void enable_x2apic_msr_intercepts(unsigned long *msr_bitmap) } } +static inline void prepare_tsc_deadline_msr_intercepts(struct vmcs12 *vmcs12, + unsigned long *msr_bitmap_l1, + unsigned long *msr_bitmap_l0) +{ + if (nested_cpu_has_guest_apic_timer(vmcs12)) { + if (vmx_test_msr_bitmap_read(msr_bitmap_l1, MSR_IA32_TSC_DEADLINE)) + vmx_set_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + else + vmx_clear_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + + if (vmx_test_msr_bitmap_write(msr_bitmap_l1, MSR_IA32_TSC_DEADLINE)) + vmx_set_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + else + vmx_clear_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + } else { + vmx_set_msr_bitmap_read(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + vmx_set_msr_bitmap_write(msr_bitmap_l0, MSR_IA32_TSC_DEADLINE); + } +} + #define BUILD_NVMX_MSR_INTERCEPT_HELPER(rw) \ static inline \ void nested_vmx_set_msr_##rw##_intercept(struct vcpu_vmx *vmx, \ @@ -701,6 +721,8 @@ static inline bool nested_vmx_prepare_msr_bitmap(struct kvm_vcpu *vcpu, } } + prepare_tsc_deadline_msr_intercepts(vmcs12, msr_bitmap_l1, msr_bitmap_l0); + /* * Always check vmcs01's bitmap to honor userspace MSR filters and any * other runtime changes to vmcs01's bitmap, e.g. dynamic pass-through. diff --git a/arch/x86/kvm/vmx/nested.h b/arch/x86/kvm/vmx/nested.h index 2a3768a194fe..9ca1df72e228 100644 --- a/arch/x86/kvm/vmx/nested.h +++ b/arch/x86/kvm/vmx/nested.h @@ -281,6 +281,11 @@ static inline bool nested_cpu_has_encls_exit(struct vmcs12 *vmcs12) return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENCLS_EXITING); } +static inline bool nested_cpu_has_guest_apic_timer(struct vmcs12 *vmcs12) +{ + return nested_cpu_has3(vmcs12, TERTIARY_EXEC_GUEST_APIC_TIMER); +} + /* * if fixed0[i] == 1: val[i] must be 1 * if fixed1[i] == 0: val[i] must be 0 -- 2.45.2