To ensure that the E825 PHY timer begins in a clean state, initiate a PHY soft reset prior to programming the PHY. This ensures that we clear any outstanding Tx timestamp memory, and ensures that the PHY internal state has been completely reset. Fixes: 7cab44f1c35f ("ice: Introduce ETH56G PHY model for E825C products") Reviewed-by: Maciek Machnikowski Tested-by: Alexander Nowlin Signed-off-by: Jacob Keller --- drivers/net/ethernet/intel/ice/ice_ptp_hw.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c index a3a9f7ce04d2..64e18fe1176b 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp_hw.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp_hw.c @@ -2120,9 +2120,11 @@ int ice_stop_phy_timer_eth56g(struct ice_hw *hw, u8 port, bool soft_reset) * @hw: pointer to the HW struct * @port: the PHY port to start * - * Start the clock of a PHY port. This must be done as part of the flow to - * re-calibrate Tx and Rx timestamping offsets whenever the clock time is - * initialized or when link speed changes. + * Perform a PHY soft reset and then start the clock for the PHY port. + * + * This must be done as part of the flow to re-calibrate Tx and Rx + * timestamping offsets whenever the clock time is initialized or when link + * speed changes. * * Return: * * %0 - success @@ -2138,6 +2140,10 @@ int ice_start_phy_timer_eth56g(struct ice_hw *hw, u8 port) tmr_idx = ice_get_ptp_src_clock_index(hw); + err = ice_ptp_phy_soft_reset_eth56g(hw, port); + if (err) + return err; + err = ice_stop_phy_timer_eth56g(hw, port, false); if (err) return err; -- 2.55.0.814.gc42f45431d0f