From: Alejandro Lucero Use cxl api for getting HPA (Host Physical Address) to use from a CXL root decoder. Signed-off-by: Alejandro Lucero Reviewed-by: Martin Habets Acked-by: Edward Cree Reviewed-by: Jonathan Cameron --- drivers/cxl/cxl.h | 15 --------------- drivers/net/ethernet/sfc/Kconfig | 1 + drivers/net/ethernet/sfc/efx_cxl.c | 27 +++++++++++++++++++++++++++ include/cxl/cxl.h | 14 ++++++++++++++ 4 files changed, 42 insertions(+), 15 deletions(-) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 076640e91ee0..ab490b5a9457 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -219,21 +219,6 @@ int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); #define CXL_RESOURCE_NONE ((resource_size_t) -1) #define CXL_TARGET_STRLEN 20 -/* - * cxl_decoder flags that define the type of memory / devices this - * decoder supports as well as configuration lock status See "CXL 2.0 - * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. - * Additionally indicate whether decoder settings were autodetected, - * user customized. - */ -#define CXL_DECODER_F_RAM BIT(0) -#define CXL_DECODER_F_PMEM BIT(1) -#define CXL_DECODER_F_TYPE2 BIT(2) -#define CXL_DECODER_F_TYPE3 BIT(3) -#define CXL_DECODER_F_LOCK BIT(4) -#define CXL_DECODER_F_ENABLE BIT(5) -#define CXL_DECODER_F_MASK GENMASK(5, 0) - enum cxl_decoder_type { CXL_DECODER_DEVMEM = 2, CXL_DECODER_HOSTONLYMEM = 3, diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig index 979f2801e2a8..e959d9b4f4ce 100644 --- a/drivers/net/ethernet/sfc/Kconfig +++ b/drivers/net/ethernet/sfc/Kconfig @@ -69,6 +69,7 @@ config SFC_MCDI_LOGGING config SFC_CXL bool "Solarflare SFC9100-family CXL support" depends on SFC && CXL_BUS >= SFC + depends on CXL_REGION default SFC help This enables SFC CXL support if the kernel is configuring CXL for diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c index 177c60b269d6..d29594e71027 100644 --- a/drivers/net/ethernet/sfc/efx_cxl.c +++ b/drivers/net/ethernet/sfc/efx_cxl.c @@ -18,6 +18,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) { struct efx_nic *efx = &probe_data->efx; struct pci_dev *pci_dev = efx->pci_dev; + resource_size_t max_size; struct efx_cxl *cxl; u16 dvsec; int rc; @@ -88,13 +89,39 @@ int efx_cxl_init(struct efx_probe_data *probe_data) return PTR_ERR(cxl->cxlmd); } + cxl->endpoint = cxl_acquire_endpoint(cxl->cxlmd); + if (IS_ERR(cxl->endpoint)) + return PTR_ERR(cxl->endpoint); + + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, + &max_size); + + if (IS_ERR(cxl->cxlrd)) { + pci_err(pci_dev, "cxl_get_hpa_freespace failed\n"); + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); + return PTR_ERR(cxl->cxlrd); + } + + if (max_size < EFX_CTPIO_BUFFER_SIZE) { + pci_err(pci_dev, "%s: not enough free HPA space %pap < %u\n", + __func__, &max_size, EFX_CTPIO_BUFFER_SIZE); + cxl_put_root_decoder(cxl->cxlrd); + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); + return -ENOSPC; + } + probe_data->cxl = cxl; + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); + return 0; } void efx_cxl_exit(struct efx_probe_data *probe_data) { + if (probe_data->cxl) + cxl_put_root_decoder(probe_data->cxl->cxlrd); } MODULE_IMPORT_NS("CXL"); diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h index 7722d4190573..788700fb1eb2 100644 --- a/include/cxl/cxl.h +++ b/include/cxl/cxl.h @@ -153,6 +153,20 @@ struct cxl_dpa_partition { #define CXL_NR_PARTITIONS_MAX 2 +/* + * cxl_decoder flags that define the type of memory / devices this + * decoder supports as well as configuration lock status See "CXL 2.0 + * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. + * Additionally indicate whether decoder settings were autodetected, + * user customized. + */ +#define CXL_DECODER_F_RAM BIT(0) +#define CXL_DECODER_F_PMEM BIT(1) +#define CXL_DECODER_F_TYPE2 BIT(2) +#define CXL_DECODER_F_TYPE3 BIT(3) +#define CXL_DECODER_F_LOCK BIT(4) +#define CXL_DECODER_F_ENABLE BIT(5) + struct cxl_memdev_ops { int (*probe)(struct cxl_memdev *cxlmd); }; -- 2.34.1