From: Ricardo Pardini The Radxa ROCK 5B / 5B+ / 5T all carry on-board Realtek RTL8125 NICs. Describe the fixed function nodes and attach ethernet0/ethernet1 aliases, so that U-Boot's fdt_fixup_ethernet() can inject mac-address properties from its ethaddr/eth1addr env, for stable MACs across boots that both U-Boot and the kernel agree on. The RTL8125 on pcie2x1l2 is shared by all three variants. The ROCK 5T additionally describes pcie2x1l1 with its second RTL8125. Signed-off-by: Ricardo Pardini --- .../arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi | 15 +++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts | 18 ++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi index bf4a1d2e55ca3..b53dfe6848cce 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-5bp-5t.dtsi @@ -10,6 +10,7 @@ / { aliases { + ethernet0 = &rtl_eth0; mmc0 = &sdhci; mmc1 = &sdmmc; mmc2 = &sdio; @@ -482,6 +483,20 @@ &pcie2x1l2 { reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l2>; status = "okay"; + + pcie@0,0 { + reg = <0x400000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x41 0x4f>; + + rtl_eth0: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x410000 0 0 0 0>; + }; + }; }; &pcie30phy { diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts index 425036146b6d9..b1a3e4b2165f9 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5t.dts @@ -8,6 +8,10 @@ / { model = "Radxa ROCK 5T"; compatible = "radxa,rock-5t", "rockchip,rk3588"; + aliases { + ethernet1 = &rtl_eth1; + }; + analog-sound { compatible = "audio-graph-card"; label = "rk3588-es8316"; @@ -76,6 +80,20 @@ &pcie2x1l1 { reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; vpcie3v3-supply = <&vcc3v3_pcie2x1l1>; status = "okay"; + + pcie@0,0 { + reg = <0x300000 0 0 0 0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; + device_type = "pci"; + bus-range = <0x31 0x3f>; + + rtl_eth1: ethernet@0,0 { + compatible = "pci10ec,8125"; + reg = <0x310000 0 0 0 0>; + }; + }; }; &pcie30phy { -- 2.54.0