The GICv5 ICH_CONTEXTR_EL2 has the IRICHPPIDIS field, which allows the hypervisor to enable/disable the HPPI selection for SPIs and LPIs. This can be used to emulate the guest enabling/disabling the IRS. Therefore, make the state of this controlled by the IRS enable state. Thus, SPIs and LPIs can't be delivered to the guest, until it enables the emulated IRS, which matches the behaviour of the real hardware. Signed-off-by: Sascha Bischoff --- arch/arm64/kvm/vgic/vgic-v5.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index 2df61426cc714..ffb0500a4c9a7 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -1058,6 +1058,7 @@ void vgic_v5_flush_ppi_state(struct kvm_vcpu *vcpu) void vgic_v5_load(struct kvm_vcpu *vcpu) { + bool irichppidis = !vcpu->kvm->arch.vgic.enabled; struct vgic_v5_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v5; u16 vm = vgic_v5_vm_id(vcpu->kvm); u16 vpe = vgic_v5_vpe_id(vcpu); @@ -1074,6 +1075,7 @@ void vgic_v5_load(struct kvm_vcpu *vcpu) kvm_call_hyp(__vgic_v5_restore_vmcr_apr, cpu_if); cpu_if->vgic_contextr = FIELD_PREP(ICH_CONTEXTR_EL2_V, true) | + FIELD_PREP(ICH_CONTEXTR_EL2_IRICHPPIDIS, irichppidis) | FIELD_PREP(ICH_CONTEXTR_EL2_VPE, vpe) | FIELD_PREP(ICH_CONTEXTR_EL2_VM, vm); -- 2.34.1