Add an ITS node below the GICv5 IRS node with the CONFIG frame as its register region. Add an MSI controller child node for the TRANSLATE frame, with a phandle and one MSI cell carrying the DeviceID. Signed-off-by: Sascha Bischoff --- arm64/gic.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arm64/gic.c b/arm64/gic.c index fca99aef..9a928e23 100644 --- a/arm64/gic.c +++ b/arm64/gic.c @@ -565,6 +565,7 @@ void gic__generate_fdt_nodes(void *fdt, struct kvm *kvm) reg_prop[2] = cpu_to_fdt64(gic_redists_base); reg_prop[3] = cpu_to_fdt64(gic_redists_size); break; + case IRQCHIP_GICV5_ITS: case IRQCHIP_GICV5: return gic__generate_gicv5_fdt_nodes(fdt, kvm); default: @@ -612,6 +613,16 @@ static void gic__generate_gicv5_fdt_nodes(void *fdt, struct kvm *kvm) cpu_to_fdt64(ARM_GICV5_IRS_SETLPI_SIZE) }; + u64 its_config_reg_prop[] = { + cpu_to_fdt64(ARM_GICV5_ITS_CONFIG_BASE), + cpu_to_fdt64(ARM_GICV5_ITS_CONFIG_SIZE), + }; + + u64 its_trans_reg_prop[] = { + cpu_to_fdt64(ARM_GICV5_ITS_TRANSL_BASE), + cpu_to_fdt64(ARM_GICV5_ITS_TRANSL_SIZE) + }; + _FDT(fdt_begin_node(fdt, "gicv5-cpuif")); _FDT(fdt_property_string(fdt, "compatible", "arm,gic-v5")); _FDT(fdt_property_cell(fdt, "#interrupt-cells", GIC_FDT_IRQ_NUM_CELLS)); @@ -646,6 +657,36 @@ static void gic__generate_gicv5_fdt_nodes(void *fdt, struct kvm *kvm) _FDT(fdt_property(fdt, "cpus", cpus, sizeof(u32) * kvm->nrcpus)); _FDT(fdt_property(fdt, "arm,iaffids", iaffids, sizeof(u16) * kvm->nrcpus)); + if (kvm->cfg.arch.irqchip == IRQCHIP_GICV5_ITS) { + /* + * GICv5 ITS node + */ + snprintf(node_at_addr, sizeof(node_at_addr), "its@%llx", + (unsigned long long)ARM_GICV5_ITS_CONFIG_BASE); + _FDT(fdt_begin_node(fdt, node_at_addr)); + _FDT(fdt_property_string(fdt, "compatible", "arm,gic-v5-its")); + _FDT(fdt_property_cell(fdt, "#address-cells", 2)); + _FDT(fdt_property_cell(fdt, "#size-cells", 2)); + _FDT(fdt_property(fdt, "ranges", NULL, 0)); + + _FDT(fdt_property(fdt, "reg", its_config_reg_prop, sizeof(its_config_reg_prop))); + _FDT(fdt_property_string(fdt, "reg-names", "ns-config")); + + snprintf(node_at_addr, sizeof(node_at_addr), "msi-controller@%llx", + (unsigned long long)ARM_GICV5_ITS_TRANSL_BASE); + _FDT(fdt_begin_node(fdt, node_at_addr)); + _FDT(fdt_property_cell(fdt, "phandle", PHANDLE_MSI)); + _FDT(fdt_property(fdt, "msi-controller", NULL, 0)); + _FDT(fdt_property_cell(fdt, "#msi-cells", 1)); + + _FDT(fdt_property(fdt, "reg", its_trans_reg_prop, sizeof(its_trans_reg_prop))); + _FDT(fdt_property_string(fdt, "reg-names", "ns-translate")); + + _FDT(fdt_end_node(fdt)); + + _FDT(fdt_end_node(fdt)); + } + _FDT(fdt_end_node(fdt)); _FDT(fdt_end_node(fdt)); -- 2.34.1