Add devicetree binding documentation for the MaxLinear LGM SoC
Ethernet controller.

Signed-off-by: Jack Ping CHNG <jchng@maxlinear.com>
---
 .../bindings/net/maxlinear,lgm-eth.yaml       | 119 ++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/net/maxlinear,lgm-eth.yaml

diff --git a/Documentation/devicetree/bindings/net/maxlinear,lgm-eth.yaml b/Documentation/devicetree/bindings/net/maxlinear,lgm-eth.yaml
new file mode 100644
index 000000000000..d613f4e535f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/maxlinear,lgm-eth.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/maxlinear,lgm-eth.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MaxLinear LGM Ethernet Controller
+
+maintainers:
+  - Jack Ping Chng <jchng@maxlinear.com>
+
+description:
+  Binding for MaxLinear LGM Ethernet controller
+
+properties:
+  compatible:
+    enum:
+      - maxlinear,lgm-eth
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: port
+      - const: ctrl
+
+  clocks:
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: ethif
+
+  resets:
+    maxItems: 1
+
+  ethernet-ports:
+    type: object
+    additionalProperties: false
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
+
+    patternProperties:
+      "^port@[0-3]$":
+        type: object
+        $ref: ethernet-controller.yaml#
+        additionalProperties: false
+
+        properties:
+          reg:
+            description: port id
+            maxItems: 1
+
+          phy-handle:
+            maxItems: 1
+
+        required:
+          - reg
+          - phy-handle
+
+  mdio:
+    $ref: mdio.yaml#
+    unevaluatedProperties: false
+
+additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - mdio
+
+examples:
+  - |
+    ethernet@e7140000 {
+        compatible = "maxlinear,lgm-eth";
+        reg = <0xe7140000 0x1200>,<0xe7150000 0x4000>;
+        reg-names = "port", "ctrl";
+        clocks = <&cgu0 32>;
+        clock-names = "ethif";
+        resets = <&rcu0 0x70 8>;
+
+        ethernet-ports {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            port@0 {
+                reg = <0>;
+                phy-handle = <&eth_phy0>;
+            };
+
+            port@1 {
+                reg = <1>;
+                phy-handle = <&eth_phy1>;
+            };
+        };
+
+        mdio {
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            eth_phy0: ethernet-phy@0 {
+                reg = <0>;
+            };
+
+            eth_phy1: ethernet-phy@1 {
+                reg = <1>;
+            };
+        };
+    };
-- 
2.34.1