According to Intel SDM 4.4.1 "Linear-Address Masking" (LAM), CR3 bits 61 (LAM_U57) and 62 (LAM_U48) are LAM control bits, not reserved. Skip the LAM control bits in the CR3 reserved-bit loops when LAM is supported for vmx_pae_test and vmx_pse_test. Fixes: 55b77db1 ("vmx: add a test for 32-bit guest PAE paging PDPTEs") Fixes: feef9d92 ("vmx: add test for 32-bit non-PAE guest") Signed-off-by: Xudong Hao --- x86/vmx_tests.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/x86/vmx_tests.c b/x86/vmx_tests.c index 16f8a648..2c0feca0 100644 --- a/x86/vmx_tests.c +++ b/x86/vmx_tests.c @@ -5896,6 +5896,11 @@ static void test_vmx_guest_pdptes(u64 cr3, u64 *pdpt) } for (b = cpuid_maxphyaddr(); b < 64; b++) { + /* CR3 bits 61 and 62 are LAM control bits, not reserved. */ + if (this_cpu_has(X86_FEATURE_LAM) && + (b == X86_CR3_LAM_U57_BIT || b == X86_CR3_LAM_U48_BIT)) + continue; + vmx_32bit_guest_init_common(cr3 | (1ull << b), pdpt); test_guest_state("CR3 reserved bit", true, (1ull << b), "bit"); } @@ -5979,6 +5984,11 @@ static void vmx_pse_test(void) } for (b = cpuid_maxphyaddr(); b < 64; b++) { + /* CR3 bits 61 and 62 are LAM control bits, not reserved. */ + if (this_cpu_has(X86_FEATURE_LAM) && + (b == X86_CR3_LAM_U57_BIT || b == X86_CR3_LAM_U48_BIT)) + continue; + vmx_32bit_guest_init_common(cr3 | (1ull << b), NULL); test_guest_state("CR3 reserved bit", true, (1ull << b), "bit"); } -- 2.52.0