The generator at CM offset 0x1d8 is not in any documentation I could find, but the firmware calls it gisb and runs it at 200 MHz off PLLD_PER with a 3.75 divider. GISB is the register bus of the STB peripherals, and on BCM2711 the GENET MDIO controller clocks its MDC from it. mdio-bcm-unimac wants that rate to work out the MDC period. Mark it critical. The firmware enables it at boot and nothing in Linux owns it, so it must never be gated. Checked on a Raspberry Pi CM4 by moving the divider at runtime, the MDIO busy time follows it. Signed-off-by: Nicolai Buchwitz --- drivers/clk/bcm/clk-bcm2835.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c index 118df86d717c6..bc1de20c7e00e 100644 --- a/drivers/clk/bcm/clk-bcm2835.c +++ b/drivers/clk/bcm/clk-bcm2835.c @@ -117,6 +117,8 @@ #define CM_EMMCDIV 0x1c4 #define CM_EMMC2CTL 0x1d0 #define CM_EMMC2DIV 0x1d4 +#define CM_GISBCTL 0x1d8 +#define CM_GISBDIV 0x1dc /* General bits for the CM_*CTL regs */ # define CM_ENABLE BIT(4) @@ -2097,6 +2099,20 @@ static const struct bcm2835_clk_desc clk_desc_array[] = { .frac_bits = 8, .tcnt_mux = 42), + /* + * GISB clock (only available for BCM2711): the STB peripheral + * register bus, set up by the firmware. The GENET MDIO controller + * derives its MDC from it. + */ + [BCM2711_CLOCK_GISB] = REGISTER_PER_CLK( + SOC_BCM2711, + .name = "gisb", + .ctl_reg = CM_GISBCTL, + .div_reg = CM_GISBDIV, + .int_bits = 4, + .frac_bits = 8, + .flags = CLK_IS_CRITICAL), + /* General purpose (GPIO) clocks */ [BCM2835_CLOCK_GP0] = REGISTER_PER_CLK( SOC_ALL, -- 2.53.0