From: Elaine Zhang Some Rockchip composite clocks use mux selector values that do not match the order of their parent clocks. Add COMPOSITE_MUXTBL to describe the parent-to-selector mapping along with the divider and gate. The RK3572 audio clocks use this layout. Signed-off-by: Elaine Zhang Signed-off-by: Cunhao Lu <1579567540@qq.com> --- Changes in v4: - Split this helper out of the RK3572 driver patch. --- drivers/clk/rockchip/clk.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h index dce4db3f67b0..bc3a1def679b 100644 --- a/drivers/clk/rockchip/clk.h +++ b/drivers/clk/rockchip/clk.h @@ -871,6 +871,28 @@ struct rockchip_clk_branch { .gate_flags = gf, \ } +#define COMPOSITE_MUXTBL(_id, cname, pnames, f, mo, ms, mw, mf, \ + mt, ds, dw, df, go, gs, gf) \ + { \ + .id = _id, \ + .branch_type = branch_composite, \ + .name = cname, \ + .parent_names = pnames, \ + .num_parents = ARRAY_SIZE(pnames), \ + .flags = f, \ + .muxdiv_offset = mo, \ + .mux_shift = ms, \ + .mux_width = mw, \ + .mux_flags = mf, \ + .mux_table = mt, \ + .div_shift = ds, \ + .div_width = dw, \ + .div_flags = df, \ + .gate_offset = go, \ + .gate_shift = gs, \ + .gate_flags = gf, \ + } + #define COMPOSITE_DIV_OFFSET(_id, cname, pnames, f, mo, ms, mw, \ mf, do, ds, dw, df, go, gs, gf) \ { \ -- 2.34.1