The Chip family specific initialization for Infineon's CYW43022 chipset. Signed-off-by: Gokul Sivakumar --- .../wireless/infineon/inffmac/chip_43022.c | 30 +++++++++++++++++++ .../wireless/infineon/inffmac/chip_43022.h | 29 ++++++++++++++++++ 2 files changed, 59 insertions(+) create mode 100644 drivers/net/wireless/infineon/inffmac/chip_43022.c create mode 100644 drivers/net/wireless/infineon/inffmac/chip_43022.h diff --git a/drivers/net/wireless/infineon/inffmac/chip_43022.c b/drivers/net/wireless/infineon/inffmac/chip_43022.c new file mode 100644 index 000000000000..a03328d1e75c --- /dev/null +++ b/drivers/net/wireless/infineon/inffmac/chip_43022.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: ISC +/* + * Copyright (c) 2024-2025, Infineon Technologies AG, or an affiliate of Infineon Technologies AG. + * All rights reserved. + */ + +#include "chip_43022.h" + +void inff_chip_43022_init(struct inff_chip *chip) +{ + struct inff_chip_specific *chip_spec = &chip->chip_spec; + struct inff_fw_dataset *fw_data = &chip_spec->fwdata[0]; + + chip_spec->hw_caps_replaycnts = INF43022_HW_CAPS_REPLAYCNTS; + chip_spec->hw_reg_pmu_status_msk = INF43022_PMU_STATUS_MASK; + chip_spec->hw_reg_pmu_ctrl_ext_msk = INF43022_PMU_CONTROL_EXT_MASK; + chip_spec->hw_chip_ramsize = INF43022_CHIP_RAMSIZE; + + fw_data[INFF_FW_CODE].fwnames.extension = ".trxs"; + fw_data[INFF_FW_CODE].fwnames.path = chip_spec->fw_name; + fw_data[INFF_FW_CODE].type = INFF_FW_TYPE_TRXS; + + fw_data[INFF_FW_NVRAM].fwnames.extension = ".txt"; + fw_data[INFF_FW_NVRAM].fwnames.path = chip_spec->nvram_name; + fw_data[INFF_FW_NVRAM].type = INFF_FW_TYPE_NVRAM; + + fw_data[INFF_FW_CLM].fwnames.extension = ".clm_blob"; + fw_data[INFF_FW_CLM].fwnames.path = chip_spec->clm_name; + fw_data[INFF_FW_CLM].type = INFF_FW_TYPE_CLM; +} diff --git a/drivers/net/wireless/infineon/inffmac/chip_43022.h b/drivers/net/wireless/infineon/inffmac/chip_43022.h new file mode 100644 index 000000000000..00715980653f --- /dev/null +++ b/drivers/net/wireless/infineon/inffmac/chip_43022.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: ISC */ +/* + * Copyright (c) 2024-2025, Infineon Technologies AG, or an affiliate of Infineon Technologies AG. + * All rights reserved. + */ + +#include "chip.h" + +/* PMU STATUS mask for 43022 */ +#define INF43022_PMU_STATUS_MASK 0x1AC + +/* PMU CONTROL EXT mask for 43002 */ +#define INF43022_PMU_CONTROL_EXT_MASK 0x11 + +/* Minimum PMU resource mask for 43022 */ +#define INF43022_PMU_MIN_RES_MASK 0xF8BFE77 + +#define INF43022_CHIP_RAMSIZE 0xA0000 + +/* chip specific settings */ +#define INF43022_HW_CAPS_REPLAYCNTS 4 + +/* INF43022 watermark expressed in number of words */ +#define INF43022_F2_WATERMARK 0x60 +#define INF43022_MES_WATERMARK 0x50 +#define INF43022_MESBUSYCTRL (INF43022_MES_WATERMARK | \ + SBSDIO_MESBUSYCTRL_ENAB) + +void inff_chip_43022_init(struct inff_chip *chip); -- 2.25.1