Systems with firmware first error handling can see heavy SMM load as a result of the mix_and_match induced IOMMU errors. For devices like igb that get wedged on these errors, the resulting FLR is delayed waiting for the transaction pending register to clear, which never occurs. However, due to the background SMM, the backoff delays in PCI code wildly exceed their timeouts. As a result, the whole test can report failure. Extend the mix_and_match timeout to a value shown to complete reliably on such systems, with ~2x margin. Assisted-by: LLM Reviewed-by: David Matlack Signed-off-by: Alex Williamson --- tools/testing/selftests/vfio/vfio_pci_driver_test.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/testing/selftests/vfio/vfio_pci_driver_test.c b/tools/testing/selftests/vfio/vfio_pci_driver_test.c index 761bf117d624..1d532f944cee 100644 --- a/tools/testing/selftests/vfio/vfio_pci_driver_test.c +++ b/tools/testing/selftests/vfio/vfio_pci_driver_test.c @@ -190,7 +190,7 @@ TEST_F(vfio_pci_driver_test, send_msi) ASSERT_EQ(1, value); } -TEST_F(vfio_pci_driver_test, mix_and_match) +TEST_F_TIMEOUT(vfio_pci_driver_test, mix_and_match, 90) { u64 value; int i; -- 2.53.0