Inside Macintosh says, "Be sure that you don't change CA0-CA2 or SEL while LSTRB is high". Unfortunately, those bits do change. The CA0-CA2 outputs become inputs when (LSTRB << 4) | LSTRB gets written to the phase register. Then LSTRB is driven low (with CA0-CA2 bits set). This is a problem because the drive interprets a STEP command as an EJECT command when these pins float high. This occurs intermittently, perhaps because interrupts are disabled and the race condition happens to end well. However, when I add code to step the heads with interrupts enabled, the disk always ejects. Keep the four phase pin directions set to output and hold their levels constant during LSTRB signalling. Introduce the PHASE_PIN_DIRECTION macro to separate the pin configuration from the logic level changes. Reviewed-by: Laurent Vivier Fixes: 8852ecd97488 ("m68k: mac - Add SWIM floppy support") Signed-off-by: Finn Thain --- Changed since v1: - Added the PHASE_PIN_DIRECTION macro to improve readability. - Re-arranged macro definition groups so as to agree with their descriptions. --- drivers/block/swim.c | 62 ++++++++++++++++++++++---------------------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/drivers/block/swim.c b/drivers/block/swim.c index 0ccc12a72388..5d89e7813049 100644 --- a/drivers/block/swim.c +++ b/drivers/block/swim.c @@ -87,37 +87,37 @@ struct iwm { #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) #define iwm_read(base, reg) in_8(&(base)->reg) -/* bits in phase register */ +/* Bits in phase register */ -#define SEEK_POSITIVE 0x070 -#define SEEK_NEGATIVE 0x074 -#define STEP 0x071 -#define MOTOR_ON 0x072 -#define MOTOR_OFF 0x076 -#define INDEX 0x073 -#define EJECT 0x077 -#define SETMFM 0x171 -#define SETGCR 0x175 - -#define RELAX 0x033 -#define LSTRB 0x008 - -#define CA_MASK 0x077 +#define RELAX 0x03 +#define LSTRB 0x08 +#define CA_MASK 0x07 +#define PHASE_PIN_DIR 0xF0 /* Select values for swim_select and swim_readbit */ -#define READ_DATA_0 0x074 -#define ONEMEG_DRIVE 0x075 -#define SINGLE_SIDED 0x076 -#define DRIVE_PRESENT 0x077 -#define DISK_IN 0x170 -#define WRITE_PROT 0x171 -#define TRACK_ZERO 0x172 -#define TACHO 0x173 -#define READ_DATA_1 0x174 -#define GCR_MODE 0x175 -#define SEEK_COMPLETE 0x176 -#define TWOMEG_MEDIA 0x177 +#define SEEK_POSITIVE 0x000 +#define SEEK_NEGATIVE 0x004 +#define STEP 0x001 +#define MOTOR_ON 0x002 +#define MOTOR_OFF 0x006 +#define INDEX 0x003 +#define EJECT 0x007 +#define SETMFM 0x101 +#define SETGCR 0x105 + +#define READ_DATA_0 0x004 +#define ONEMEG_DRIVE 0x005 +#define SINGLE_SIDED 0x006 +#define DRIVE_PRESENT 0x007 +#define DISK_IN 0x100 +#define WRITE_PROT 0x101 +#define TRACK_ZERO 0x102 +#define TACHO 0x103 +#define READ_DATA_1 0x104 +#define GCR_MODE 0x105 +#define SEEK_COMPLETE 0x106 +#define TWOMEG_MEDIA 0x107 /* Bits in handshake register */ @@ -269,11 +269,11 @@ static inline int get_swim_mode(struct swim __iomem *base) static inline void swim_select(struct swim __iomem *base, int sel) { - swim_write(base, phase, RELAX); + swim_write(base, phase, RELAX | PHASE_PIN_DIR); via1_set_head(sel & 0x100); - swim_write(base, phase, sel & CA_MASK); + swim_write(base, phase, (sel & CA_MASK) | PHASE_PIN_DIR); } static inline void swim_action(struct swim __iomem *base, int action) @@ -284,9 +284,9 @@ static inline void swim_action(struct swim __iomem *base, int action) swim_select(base, action); udelay(1); - swim_write(base, phase, (LSTRB<<4) | LSTRB); + swim_write(base, phase, LSTRB | action | PHASE_PIN_DIR); udelay(1); - swim_write(base, phase, (LSTRB<<4) | ((~LSTRB) & 0x0F)); + swim_write(base, phase, action | PHASE_PIN_DIR); udelay(1); local_irq_restore(flags); -- 2.52.0