From: Irving-CH Lin Add support for the MT8189 vcodec clock controller, which provides clock gate control for video encoder/decoder. Signed-off-by: Irving-CH Lin --- drivers/clk/mediatek/Kconfig | 10 +++ drivers/clk/mediatek/Makefile | 1 + drivers/clk/mediatek/clk-mt8189-vcodec.c | 93 ++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 drivers/clk/mediatek/clk-mt8189-vcodec.c diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig index 3ef964b19d97..2ae5966d4c56 100644 --- a/drivers/clk/mediatek/Kconfig +++ b/drivers/clk/mediatek/Kconfig @@ -951,6 +951,16 @@ config COMMON_CLK_MT8189_UFS option if the system includes a UFS device that relies on the MT8189 SoC for clock management. +config COMMON_CLK_MT8189_VCODEC + tristate "Clock driver for MediaTek MT8189 vcodec" + depends on COMMON_CLK_MT8189 + default COMMON_CLK_MT8189 + help + This driver supports the video codec (VCODEC) clocks on the MediaTek + MT8189 SoCs. Enabling this option will allow the system to manage + clocks required for the operation of hardware video encoding and + decoding features provided by the VCODEC unit of the MT8189 platform. + config COMMON_CLK_MT8192 tristate "Clock driver for MediaTek MT8192" depends on ARM64 || COMPILE_TEST diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile index 4179808dba7b..614371c92e81 100644 --- a/drivers/clk/mediatek/Makefile +++ b/drivers/clk/mediatek/Makefile @@ -136,6 +136,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_MFG) += clk-mt8189-mfg.o obj-$(CONFIG_COMMON_CLK_MT8189_MMSYS) += clk-mt8189-dispsys.o obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o obj-$(CONFIG_COMMON_CLK_MT8189_UFS) += clk-mt8189-ufs.o +obj-$(CONFIG_COMMON_CLK_MT8189_VCODEC) += clk-mt8189-vcodec.o obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o diff --git a/drivers/clk/mediatek/clk-mt8189-vcodec.c b/drivers/clk/mediatek/clk-mt8189-vcodec.c new file mode 100644 index 000000000000..87b01e432474 --- /dev/null +++ b/drivers/clk/mediatek/clk-mt8189-vcodec.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2025 MediaTek Inc. + * Author: Qiqi Wang + */ + +#include +#include +#include +#include + +#include "clk-mtk.h" +#include "clk-gate.h" + +#include + +static const struct mtk_gate_regs vdec_core0_cg_regs = { + .set_ofs = 0x0, + .clr_ofs = 0x4, + .sta_ofs = 0x0, +}; + +static const struct mtk_gate_regs vdec_core1_cg_regs = { + .set_ofs = 0x8, + .clr_ofs = 0xc, + .sta_ofs = 0x8, +}; + +#define GATE_VDEC_CORE0(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdec_core0_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr_inv, CLK_IGNORE_UNUSED) + +#define GATE_VDEC_CORE1(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &vdec_core1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr_inv, CLK_IGNORE_UNUSED) + +static const struct mtk_gate vdec_core_clks[] = { + /* VDEC_CORE0 */ + GATE_VDEC_CORE0(CLK_VDEC_CORE_VDEC_CKEN, "vdec_core_vdec_cken", "vdec_sel", 0), + GATE_VDEC_CORE0(CLK_VDEC_CORE_VDEC_ACTIVE, "vdec_core_vdec_active", "vdec_sel", 4), + /* VDEC_CORE1 */ + GATE_VDEC_CORE1(CLK_VDEC_CORE_LARB_CKEN, "vdec_core_larb_cken", "vdec_sel", 0), +}; + +static const struct mtk_clk_desc vdec_core_mcd = { + .clks = vdec_core_clks, + .num_clks = ARRAY_SIZE(vdec_core_clks), +}; + +static const struct mtk_gate_regs ven1_cg_regs = { + .set_ofs = 0x4, + .clr_ofs = 0x8, + .sta_ofs = 0x0, +}; + +#define GATE_VEN1(_id, _name, _parent, _shift) \ + GATE_MTK_FLAGS(_id, _name, _parent, &ven1_cg_regs, _shift, \ + &mtk_clk_gate_ops_setclr_inv, CLK_IGNORE_UNUSED) + +static const struct mtk_gate ven1_clks[] = { + GATE_VEN1(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc_sel", 0), + GATE_VEN1(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc_sel", 4), + GATE_VEN1(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc_sel", 8), + GATE_VEN1(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc_sel", 12), + GATE_VEN1(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc_sel", 16), + GATE_VEN1(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc_sel", 28), + GATE_VEN1(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc_sel", 31), +}; + +static const struct mtk_clk_desc ven1_mcd = { + .clks = ven1_clks, + .num_clks = ARRAY_SIZE(ven1_clks), +}; + +static const struct of_device_id of_match_clk_mt8189_vcodec[] = { + { .compatible = "mediatek,mt8189-vdec-core", .data = &vdec_core_mcd }, + { .compatible = "mediatek,mt8189-venc", .data = &ven1_mcd }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_vcodec); + +static struct platform_driver clk_mt8189_vcodec_drv = { + .probe = mtk_clk_simple_probe, + .remove = mtk_clk_simple_remove, + .driver = { + .name = "clk-mt8189-vcodec", + .of_match_table = of_match_clk_mt8189_vcodec, + }, +}; + +module_platform_driver(clk_mt8189_vcodec_drv); +MODULE_DESCRIPTION("MediaTek MT8189 video encoder/decoder clocks driver"); +MODULE_LICENSE("GPL"); -- 2.45.2