When #size-cells > 1 it is preferred to have each entry as its own
tuple, to make it easier to identify addresses and sizes. Update
artpec6.dtsi to use preferred style to increase readability.

Signed-off-by: Henrik Grimler <henrik.grimler@axis.com>
---
 arch/arm/boot/dts/axis/artpec6.dtsi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boot/dts/axis/artpec6.dtsi b/arch/arm/boot/dts/axis/artpec6.dtsi
index d6610f62ca25..49439058854d 100644
--- a/arch/arm/boot/dts/axis/artpec6.dtsi
+++ b/arch/arm/boot/dts/axis/artpec6.dtsi
@@ -161,17 +161,17 @@ pmu {
 	 */
 	pcie: pcie@f8050000 {
 		compatible = "axis,artpec6-pcie", "snps,dw-pcie";
-		reg = <0xf8050000 0x2000
-		       0xf8040000 0x1000
-		       0xc0000000 0x2000>;
+		reg = <0xf8050000 0x2000>,
+		      <0xf8040000 0x1000>,
+		      <0xc0000000 0x2000>;
 		reg-names = "dbi", "phy", "config";
 		#address-cells = <3>;
 		#size-cells = <2>;
 		device_type = "pci";
 			  /* downstream I/O */
-		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000
+		ranges = <0x81000000 0 0 0xc0002000 0 0x00010000>,
 			  /* non-prefetchable memory */
-			  0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
+			 <0x82000000 0 0xc0012000 0xc0012000 0 0x1ffee000>;
 		num-lanes = <2>;
 		bus-range = <0x00 0xff>;
 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
@@ -188,10 +188,10 @@ pcie: pcie@f8050000 {
 
 	pcie_ep: pcie-ep@f8050000 {
 		compatible = "axis,artpec6-pcie-ep", "snps,dw-pcie";
-		reg = <0xf8050000 0x2000
-		       0xf8051000 0x2000
-		       0xf8040000 0x1000
-		       0xc0000000 0x20000000>;
+		reg = <0xf8050000 0x2000>,
+		      <0xf8051000 0x2000>,
+		      <0xf8040000 0x1000>,
+		      <0xc0000000 0x20000000>;
 		reg-names = "dbi", "dbi2", "phy", "addr_space";
 		num-ib-windows = <6>;
 		num-ob-windows = <2>;

-- 
2.43.0