From: Javen Xu This patch adds ltr support for RTL8116af, enables RTL8116af enter l1.2 state. This makes sense for the system to enter c10 state. Signed-off-by: Javen Xu --- drivers/net/ethernet/realtek/r8169_main.c | 31 +++++++++++++++++++---- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/drivers/net/ethernet/realtek/r8169_main.c b/drivers/net/ethernet/realtek/r8169_main.c index 58788d196c57..fb2247a20c36 100644 --- a/drivers/net/ethernet/realtek/r8169_main.c +++ b/drivers/net/ethernet/realtek/r8169_main.c @@ -330,11 +330,13 @@ enum rtl_registers { ALDPS_LTR = 0xe0a2, LTR_OBFF_LOCK = 0xe032, LTR_SNOOP = 0xe034, + SEND_LTR_MSG = 0xe038, #define ALDPS_LTR_EN BIT(0) #define LTR_OBFF_LOCK_EN BIT(0) #define LINK_SPEED_CHANGE_EN BIT(14) #define LTR_SNOOP_EN GENMASK(15, 14) +#define LTR_MSG_EN BIT(0) }; enum rtl8168_8101_registers { @@ -3093,8 +3095,22 @@ static void rtl_enable_ltr(struct rtl8169_private *tp) r8168_mac_ocp_write(tp, 0xcdf2, 0x9003); r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0000, LINK_SPEED_CHANGE_EN); break; - case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: case RTL_GIGA_MAC_VER_52: + r8168_mac_ocp_write(tp, 0xcdd0, 0x9003); + r8168_mac_ocp_modify(tp, LTR_SNOOP, 0x0000, LTR_SNOOP_EN); + r8168_mac_ocp_write(tp, 0xe02c, 0x1880); + r8168_mac_ocp_write(tp, 0xe02e, 0x4880); + r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); + r8168_mac_ocp_write(tp, 0xcdd8, 0x9003); + r8168_mac_ocp_write(tp, 0xcdda, 0x9003); + r8168_mac_ocp_write(tp, 0xcddc, 0x9003); + r8168_mac_ocp_write(tp, 0xcdd2, 0x883c); + r8168_mac_ocp_write(tp, 0xcdd4, 0x8c12); + r8168_mac_ocp_write(tp, 0xcdd6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a6, 0x9003); + r8168_mac_ocp_write(tp, 0xe0a8, 0x9003); + break; + case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: r8168_mac_ocp_modify(tp, ALDPS_LTR, 0x0000, ALDPS_LTR_EN); RTL_W8(tp, COMBO_LTR_EXTEND, RTL_R8(tp, COMBO_LTR_EXTEND) | COMBO_LTR_EXTEND_EN); fallthrough; @@ -3114,6 +3130,7 @@ static void rtl_enable_ltr(struct rtl8169_private *tp) } /* chip can trigger LTR */ r8168_mac_ocp_modify(tp, LTR_OBFF_LOCK, 0x0003, LTR_OBFF_LOCK_EN); + r8168_mac_ocp_modify(tp, SEND_LTR_MSG, 0x0000, LTR_MSG_EN); } static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) @@ -3147,6 +3164,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) rtl_enable_ltr(tp); switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: /* reset ephy tx/rx disable timer */ r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); @@ -3159,6 +3177,7 @@ static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable) } else { switch (tp->mac_version) { case RTL_GIGA_MAC_VER_46 ... RTL_GIGA_MAC_VER_48: + case RTL_GIGA_MAC_VER_52: case RTL_GIGA_MAC_VER_61 ... RTL_GIGA_MAC_VER_LAST: r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); break; @@ -3672,7 +3691,9 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp) rtl_eri_set_bits(tp, 0xd4, 0x0010); - rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); + rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4000); + + r8168_mac_ocp_write(tp, 0xe098, 0xc302); rtl_disable_rxdvgate(tp); @@ -3697,9 +3718,9 @@ static void rtl_hw_start_8117(struct rtl8169_private *tp) } r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0000); - r8168_mac_ocp_write(tp, 0xea80, 0x0003); - r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); - r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); + r8168_mac_ocp_write(tp, 0xea80, 0x0000); + r8168_mac_ocp_modify(tp, 0xe052, 0x0009, 0x0000); + r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x045f); r8168_mac_ocp_write(tp, 0xe63e, 0x0001); r8168_mac_ocp_write(tp, 0xe63e, 0x0000); -- 2.43.0