From: Mohamed Mediouni When starting up the VM at EL2, more sysregs are available. Sync the state of those. Signed-off-by: Mohamed Mediouni [PMD: Adapted to host_cpu_feature_supported() API] Signed-off-by: Philippe Mathieu-Daudé --- target/arm/hvf/hvf.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 5174973991f..778dc3cedf7 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -400,6 +400,7 @@ static const struct hvf_reg_match hvf_fpreg_match[] = { struct hvf_sreg_match { int reg; uint32_t key; + bool el2; uint32_t cp_idx; }; @@ -545,6 +546,27 @@ static struct hvf_sreg_match hvf_sreg_match[] = { { HV_SYS_REG_CNTV_CTL_EL0, HVF_SYSREG(14, 3, 3, 3, 1) }, { HV_SYS_REG_CNTV_CVAL_EL0, HVF_SYSREG(14, 3, 3, 3, 2) }, { HV_SYS_REG_SP_EL1, HVF_SYSREG(4, 1, 3, 4, 0) }, + /* EL2 */ + { HV_SYS_REG_CPTR_EL2, HVF_SYSREG(1, 1, 3, 4, 2), .el2 = true }, + { HV_SYS_REG_ELR_EL2, HVF_SYSREG(4, 0, 3, 4, 1), .el2 = true }, + { HV_SYS_REG_ESR_EL2, HVF_SYSREG(5, 2, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_FAR_EL2, HVF_SYSREG(6, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_HCR_EL2, HVF_SYSREG(1, 1, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_HPFAR_EL2, HVF_SYSREG(6, 0, 3, 4, 4), .el2 = true }, + { HV_SYS_REG_MAIR_EL2, HVF_SYSREG(10, 2, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_MDCR_EL2, HVF_SYSREG(1, 1, 3, 4, 1), .el2 = true }, + { HV_SYS_REG_SCTLR_EL2, HVF_SYSREG(1, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_SPSR_EL2, HVF_SYSREG(4, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_SP_EL2, HVF_SYSREG(4, 1, 3, 6, 0), .el2 = true}, + { HV_SYS_REG_TCR_EL2, HVF_SYSREG(2, 0, 3, 4, 2), .el2 = true }, + { HV_SYS_REG_TPIDR_EL2, HVF_SYSREG(13, 0, 3, 4, 2), .el2 = true }, + { HV_SYS_REG_TTBR0_EL2, HVF_SYSREG(2, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_TTBR1_EL2, HVF_SYSREG(2, 0, 3, 4, 1), .el2 = true }, + { HV_SYS_REG_VBAR_EL2, HVF_SYSREG(12, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_VMPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 5), .el2 = true }, + { HV_SYS_REG_VPIDR_EL2, HVF_SYSREG(0, 0, 3, 4, 0), .el2 = true }, + { HV_SYS_REG_VTCR_EL2, HVF_SYSREG(2, 1, 3, 4, 2), .el2 = true }, + { HV_SYS_REG_VTTBR_EL2, HVF_SYSREG(2, 1, 3, 4, 0), .el2 = true }, }; int hvf_get_registers(CPUState *cpu) @@ -588,6 +610,12 @@ int hvf_get_registers(CPUState *cpu) continue; } + if (hvf_sreg_match[i].el2 + && arm_feature(env, ARM_FEATURE_EL2) + && !host_cpu_feature_supported(ARM_FEATURE_EL2, false)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { @@ -725,6 +753,12 @@ int hvf_put_registers(CPUState *cpu) continue; } + if (hvf_sreg_match[i].el2 + && arm_feature(env, ARM_FEATURE_EL2) + && !host_cpu_feature_supported(ARM_FEATURE_EL2, false)) { + continue; + } + if (cpu->accel->guest_debug_enabled) { /* Handle debug registers */ switch (hvf_sreg_match[i].reg) { -- 2.49.0