The entries of the L2 service code table are 0x20 apart on IPQ5424, instead of 0x10 on IPQ9574. Each IPQ5424 entry also has a second word holding the extended egress bypass bitmap, which adds the bypass of the source MAC multicast drop, L2 flooding and tunnel exception counter control. Add the L2 service code table stride and the extended egress bypass bitmap for IPQ5424. Signed-off-by: Luo Jie --- drivers/net/ethernet/qualcomm/ppe/ppe_config.c | 13 ++++++++++--- drivers/net/ethernet/qualcomm/ppe/ppe_config.h | 4 ++++ drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 12 +++++++++++- 3 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c index 83e1f2d30258..94885240166b 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c @@ -1476,7 +1476,7 @@ int ppe_port_resource_get(struct ppe_device *ppe_dev, int port, */ int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cfg cfg) { - u32 val, reg, servcode_val[2] = {}; + u32 val, reg, servcode_val[2] = {}, in_l2_val[2] = {}; unsigned long bitmap_value; int ret; @@ -1490,9 +1490,16 @@ int ppe_sc_config_set(struct ppe_device *ppe_dev, int sc, struct ppe_sc_cfg cfg) test_bit(PPE_SC_BYPASS_COUNTER_RX, cfg.bitmaps.counter)); val |= FIELD_PREP(PPE_IN_L2_SERVICE_TBL_TX_CNT_EN, test_bit(PPE_SC_BYPASS_COUNTER_TX, cfg.bitmaps.counter)); - reg = PPE_IN_L2_SERVICE_TBL_ADDR + PPE_IN_L2_SERVICE_TBL_INC * sc; + reg = PPE_IN_L2_SERVICE_TBL_ADDR + PPE_IN_L2_SERVICE_TBL_INC(ppe_dev) * sc; - ret = regmap_write(ppe_dev->regmap, reg, val); + in_l2_val[0] = val; + + bitmap_value = bitmap_read(cfg.bitmaps.egress, PPE_SC_BYPASS_EGRESS_SMAC_MC_DROP, + PPE_SC_BYPASS_EGRESS_SIZE - PPE_SC_BYPASS_EGRESS_SMAC_MC_DROP); + in_l2_val[1] = FIELD_PREP(PPE_IN_L2_SERVICE_TBL_W1_BYPASS_BITMAP_EXT, bitmap_value); + + ret = regmap_bulk_write(ppe_dev->regmap, reg, in_l2_val, + PPE_IN_L2_SERVICE_TBL_WORDS(ppe_dev)); if (ret) return ret; diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h index 60493e51e0a4..e7cdab9d963a 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.h @@ -163,6 +163,10 @@ enum ppe_sc_egress_type { PPE_SC_BYPASS_EGRESS_FAKE_MAC_DROP = 21, PPE_SC_BYPASS_EGRESS_TUNL_CONTEXT = 22, PPE_SC_BYPASS_EGRESS_FLOW_POLICER = 23, + /* Values 24-26 are only supported by IPQ5424. */ + PPE_SC_BYPASS_EGRESS_SMAC_MC_DROP = 24, + PPE_SC_BYPASS_EGRESS_L2_FLOODING = 25, + PPE_SC_BYPASS_EGRESS_TUNNEL_EXP_CNT_CTRL = 26, /* This must be last as it determines the size of the BITMAP. */ PPE_SC_BYPASS_EGRESS_SIZE, }; diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h index 441e8e04a80b..089aa34b7732 100644 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h @@ -223,13 +223,23 @@ /* PPE service code configuration for destination port and counter. */ #define PPE_IN_L2_SERVICE_TBL_ADDR 0x66000 #define PPE_IN_L2_SERVICE_TBL_ENTRIES 256 -#define PPE_IN_L2_SERVICE_TBL_INC 0x10 +#define PPE_IN_L2_SERVICE_TBL_IPQ9574_INC 0x10 +#define PPE_IN_L2_SERVICE_TBL_IPQ5424_INC 0x20 +#define PPE_IN_L2_SERVICE_TBL_INC(ppe_dev) \ + ((ppe_dev)->type == IPQ5424_PPE ? PPE_IN_L2_SERVICE_TBL_IPQ5424_INC : \ + PPE_IN_L2_SERVICE_TBL_IPQ9574_INC) +#define PPE_IN_L2_SERVICE_TBL_IPQ9574_WORDS 1 +#define PPE_IN_L2_SERVICE_TBL_IPQ5424_WORDS 2 +#define PPE_IN_L2_SERVICE_TBL_WORDS(ppe_dev) \ + ((ppe_dev)->type == IPQ5424_PPE ? PPE_IN_L2_SERVICE_TBL_IPQ5424_WORDS : \ + PPE_IN_L2_SERVICE_TBL_IPQ9574_WORDS) #define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID_VALID BIT(0) #define PPE_IN_L2_SERVICE_TBL_DST_PORT_ID GENMASK(4, 1) #define PPE_IN_L2_SERVICE_TBL_DST_DIRECTION BIT(5) #define PPE_IN_L2_SERVICE_TBL_DST_BYPASS_BITMAP GENMASK(29, 6) #define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30) #define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31) +#define PPE_IN_L2_SERVICE_TBL_W1_BYPASS_BITMAP_EXT GENMASK(7, 0) /* L2 Port configurations */ #define PPE_L2_VP_PORT_TBL_ADDR 0x98000 -- 2.43.0