Add the GP M/N clock controller and its pin configuration for SA8775P. The controller uses the PDM XO4 and AHB clocks from GCC and routes its output to gpio35. Signed-off-by: Taniya Das --- arch/arm64/boot/dts/qcom/lemans.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 1fdb72fa5518446ba2ea582e8362e86bba75c379..4132d288e3a16ab0a6d8b6d0816e85671bd25c73 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -4348,6 +4348,20 @@ opp-384000000 { }; }; + gp_mn: clock-controller@88d3000 { + compatible = "qcom,sa8775p-gp-mnd", "qcom,sc7280-gp-mnd"; + reg = <0x0 0x088d3000 0x0 0x1000>; + clocks = <&gcc GCC_PDM_XO4_CLK>, + <&gcc GCC_PDM_AHB_CLK>; + clock-names = "pdm_clk", "ahb_clk"; + #clock-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&gp_mn_active>; + assigned-clocks = <&gcc GCC_PDM_XO4_CLK>; + assigned-clock-rates = <4800000>; + status = "disabled"; + }; + usb_0_hsphy: phy@88e4000 { compatible = "qcom,sa8775p-usb-hs-phy", "qcom,usb-snps-hs-5nm-phy"; @@ -6017,6 +6031,13 @@ dp1_hot_plug_det: dp1-hot-plug-det-state { bias-disable; }; + gp_mn_active: gp-mn-active-state { + pins = "gpio35"; + function = "gp_mn"; + drive-strength = <2>; + bias-disable; + }; + hs0_mi2s_active: hs0-mi2s-active-state { pins = "gpio114", "gpio115", "gpio116", "gpio117"; function = "hs0_mi2s"; -- 2.34.1