Enable port shaping and support limiting the rate of outgoing traffic. Signed-off-by: David Yang --- drivers/net/dsa/yt921x.c | 120 +++++++++++++++++++++++++++++++++++++++ drivers/net/dsa/yt921x.h | 67 +++++++++++++++++++++- 2 files changed, 186 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/yt921x.c b/drivers/net/dsa/yt921x.c index 6fa70cea0631..48b322185124 100644 --- a/drivers/net/dsa/yt921x.c +++ b/drivers/net/dsa/yt921x.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "yt921x.h" @@ -1304,6 +1305,110 @@ yt921x_dsa_port_policer_add(struct dsa_switch *ds, int port, return res; } +static int +yt921x_tbf_validate(struct yt921x_priv *priv, + const struct tc_tbf_qopt_offload *qopt, int *queuep) +{ + struct device *dev = to_device(priv); + int queue = -1; + + if (qopt->parent != TC_H_ROOT) { + dev_err(dev, "Parent should be \"root\"\n"); + return -EOPNOTSUPP; + } + + switch (qopt->command) { + case TC_TBF_REPLACE: { + const struct tc_tbf_qopt_offload_replace_params *p; + + p = &qopt->replace_params; + + if (!p->rate.mpu) { + dev_info(dev, "Assuming you want mpu = 64\n"); + } else if (p->rate.mpu != 64) { + dev_err(dev, "mpu other than 64 not supported\n"); + return -EINVAL; + } + } + default: + break; + } + + *queuep = queue; + return 0; +} + +static int +yt921x_dsa_port_setup_tc_tbf_port(struct dsa_switch *ds, int port, + const struct tc_tbf_qopt_offload *qopt) +{ + struct yt921x_priv *priv = to_yt921x_priv(ds); + u32 ctrls[YT921X_PORT_SHAPE_CTRL_S]; + int res; + + switch (qopt->command) { + case TC_TBF_DESTROY: + ctrls[0] = 0; + ctrls[1] = 0; + break; + case TC_TBF_REPLACE: { + const struct tc_tbf_qopt_offload_replace_params *p; + struct yt921x_meter meter; + u64 burst; + + p = &qopt->replace_params; + + /* where is burst??? */ + burst = priv->port_shape_slot_ns * p->rate.rate_bytes_ps / + 1000000000 + 10000; + meter = yt921x_meter_tfm(priv, port, priv->port_shape_slot_ns, + p->rate.rate_bytes_ps, burst, + YT921X_METER_SINGLE_BUCKET, + YT921X_SHAPE_RATE_MAX, + YT921X_SHAPE_BURST_MAX, + YT921X_SHAPE_UNIT_MAX); + + ctrls[0] = YT921X_PORT_SHAPE_CTRLa_CIR(meter.cir) | + YT921X_PORT_SHAPE_CTRLa_CBS(meter.cbs); + ctrls[1] = YT921X_PORT_SHAPE_CTRLb_UNIT(meter.unit) | + YT921X_PORT_SHAPE_CTRLb_EN; + break; + } + default: + return -EOPNOTSUPP; + } + + mutex_lock(&priv->reg_lock); + res = yt921x_longreg_write(priv, YT921X_PORTn_SHAPE_CTRL(port), + ctrls, YT921X_PORT_SHAPE_CTRL_S); + mutex_unlock(&priv->reg_lock); + + return res; +} + +static int +yt921x_dsa_port_setup_tc(struct dsa_switch *ds, int port, + enum tc_setup_type type, void *type_data) +{ + struct yt921x_priv *priv = to_yt921x_priv(ds); + int res; + + switch (type) { + case TC_SETUP_QDISC_TBF: { + const struct tc_tbf_qopt_offload *qopt = type_data; + int queue; + + res = yt921x_tbf_validate(priv, qopt, &queue); + if (res) + return res; + + return yt921x_dsa_port_setup_tc_tbf_port(ds, port, qopt); + } + default: + return -EOPNOTSUPP; + } +} + static int yt921x_mirror_del(struct yt921x_priv *priv, int port, bool ingress) { @@ -3465,6 +3570,20 @@ static int yt921x_chip_setup_tc(struct yt921x_priv *priv) return res; priv->meter_slot_ns = ctrl * op_ns; + ctrl = max(priv->port_shape_slot_ns / op_ns, + YT921X_PORT_SHAPE_SLOT_MIN); + res = yt921x_reg_write(priv, YT921X_PORT_SHAPE_SLOT, ctrl); + if (res) + return res; + priv->port_shape_slot_ns = ctrl * op_ns; + + ctrl = max(priv->queue_shape_slot_ns / op_ns, + YT921X_QUEUE_SHAPE_SLOT_MIN); + res = yt921x_reg_write(priv, YT921X_QUEUE_SHAPE_SLOT, ctrl); + if (res) + return res; + priv->queue_shape_slot_ns = ctrl * op_ns; + return 0; } @@ -3621,6 +3740,7 @@ static const struct dsa_switch_ops yt921x_dsa_switch_ops = { /* rate */ .port_policer_del = yt921x_dsa_port_policer_del, .port_policer_add = yt921x_dsa_port_policer_add, + .port_setup_tc = yt921x_dsa_port_setup_tc, /* hsr */ .port_hsr_leave = dsa_port_simple_hsr_leave, .port_hsr_join = dsa_port_simple_hsr_join, diff --git a/drivers/net/dsa/yt921x.h b/drivers/net/dsa/yt921x.h index b033b942b394..e18216996ee9 100644 --- a/drivers/net/dsa/yt921x.h +++ b/drivers/net/dsa/yt921x.h @@ -526,6 +526,12 @@ enum yt921x_app_selector { #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_TAGGED BIT(1) #define YT921X_PORT_VLAN_CTRL1_CVLAN_DROP_UNTAGGED BIT(0) +#define YT921X_PORTn_PRIO_UCAST_QUEUE(port) (0x300200 + 4 * (port)) +#define YT921X_PORT_PRIOm_UCAST_QUEUE_M(m) (7 << (3 * (m))) +#define YT921X_PORT_PRIOm_UCAST_QUEUE(m, x) ((x) << (3 * (m))) +#define YT921X_PORTn_PRIO_MCAST_QUEUE(port) (0x300280 + 4 * (port)) +#define YT921X_PORT_PRIOm_MCAST_QUEUE_M(m) (3 << (2 * (m))) +#define YT921X_PORT_PRIOm_MCAST_QUEUE(m, x) ((x) << (2 * (m))) #define YT921X_MIRROR 0x300300 #define YT921X_MIRROR_IGR_PORTS_M GENMASK(26, 16) #define YT921X_MIRROR_IGR_PORTS(x) FIELD_PREP(YT921X_MIRROR_IGR_PORTS_M, (x)) @@ -536,6 +542,49 @@ enum yt921x_app_selector { #define YT921X_MIRROR_PORT_M GENMASK(3, 0) #define YT921X_MIRROR_PORT(x) FIELD_PREP(YT921X_MIRROR_PORT_M, (x)) +#define YT921X_QUEUE_SHAPE_SLOT 0x340008 +#define YT921X_QUEUE_SHAPE_SLOT_SLOT_M GENMASK(11, 0) +#define YT921X_PORT_SHAPE_SLOT 0x34000c +#define YT921X_PORT_SHAPE_SLOT_SLOT_M GENMASK(11, 0) +#define YT921X_QUEUEn_SCH(x) (0x341000 + 4 * (x)) +#define YT921X_QUEUE_SCH_E_DWRR_M GENMASK(27, 18) +#define YT921X_QUEUE_SCH_E_DWRR(x) FIELD_PREP(YT921X_QUEUE_SCH_E_DWRR_M, (x)) +#define YT921X_QUEUE_SCH_C_DWRR_M GENMASK(17, 8) +#define YT921X_QUEUE_SCH_C_DWRR(x) FIELD_PREP(YT921X_QUEUE_SCH_C_DWRR_M, (x)) +#define YT921X_QUEUE_SCH_E_PRIO_M GENMASK(7, 4) +#define YT921X_QUEUE_SCH_E_PRIO(x) FIELD_PREP(YT921X_QUEUE_SCH_E_PRIO_M, (x)) +#define YT921X_QUEUE_SCH_C_PRIO_M GENMASK(3, 0) +#define YT921X_QUEUE_SCH_C_PRIO(x) FIELD_PREP(YT921X_QUEUE_SCH_C_PRIO_M, (x)) +#define YT921X_C_DWRRn(x) (0x342000 + 4 * (x)) +#define YT921X_E_DWRRn(x) (0x343000 + 4 * (x)) +#define YT921X_DWRR_PKT_MODE BIT(0) /* 0: byte rate mode */ +#define YT921X_QUEUEn_SHAPE_CTRL(x) (0x34c000 + 0x10 * (x)) +#define YT921X_QUEUE_SHAPE_CTRL_S 3 +#define YT921X_QUEUE_SHAPE_CTRLc_TOKEN_OVERFLOW_EN BIT(6) +#define YT921X_QUEUE_SHAPE_CTRLc_E_EN BIT(5) +#define YT921X_QUEUE_SHAPE_CTRLc_C_EN BIT(4) +#define YT921X_QUEUE_SHAPE_CTRLc_PKT_MODE BIT(3) /* 0: byte rate mode */ +#define YT921X_QUEUE_SHAPE_CTRLc_UNIT_M GENMASK(2, 0) +#define YT921X_QUEUE_SHAPE_CTRLc_UNIT(x) FIELD_PREP(YT921X_QUEUE_SHAPE_CTRLc_UNIT_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLb_EBS_M GENMASK(31, 18) +#define YT921X_QUEUE_SHAPE_CTRLb_EBS(x) FIELD_PREP(YT921X_QUEUE_SHAPE_CTRLb_EBS_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLb_EIR_M GENMASK(17, 0) +#define YT921X_QUEUE_SHAPE_CTRLb_EIR(x) FIELD_PREP(YT921X_QUEUE_SHAPE_CTRLb_EIR_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLa_CBS_M GENMASK(31, 18) +#define YT921X_QUEUE_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_QUEUE_SHAPE_CTRLa_CBS_M, (x)) +#define YT921X_QUEUE_SHAPE_CTRLa_CIR_M GENMASK(17, 0) +#define YT921X_QUEUE_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_QUEUE_SHAPE_CTRLa_CIR_M, (x)) +#define YT921X_PORTn_SHAPE_CTRL(port) (0x354000 + 8 * (port)) +#define YT921X_PORT_SHAPE_CTRL_S 2 +#define YT921X_PORT_SHAPE_CTRLb_EN BIT(4) +#define YT921X_PORT_SHAPE_CTRLb_PKT_MODE BIT(3) /* 0: byte rate mode */ +#define YT921X_PORT_SHAPE_CTRLb_UNIT_M GENMASK(2, 0) +#define YT921X_PORT_SHAPE_CTRLb_UNIT(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLb_UNIT_M, (x)) +#define YT921X_PORT_SHAPE_CTRLa_CBS_M GENMASK(31, 18) +#define YT921X_PORT_SHAPE_CTRLa_CBS(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CBS_M, (x)) +#define YT921X_PORT_SHAPE_CTRLa_CIR_M GENMASK(17, 0) +#define YT921X_PORT_SHAPE_CTRLa_CIR(x) FIELD_PREP(YT921X_PORT_SHAPE_CTRLa_CIR_M, (x)) + #define YT921X_EDATA_EXTMODE 0xfb #define YT921X_EDATA_LEN 0x100 @@ -561,6 +610,11 @@ enum yt921x_fdb_entry_status { #define YT921X_METER_UNIT_MAX ((1 << 3) - 1) #define YT921X_METER_BURST_MAX ((1 << 16) - 1) #define YT921X_METER_RATE_MAX ((1 << 18) - 1) +#define YT921X_PORT_SHAPE_SLOT_MIN 80 +#define YT921X_QUEUE_SHAPE_SLOT_MIN 132 +#define YT921X_SHAPE_UNIT_MAX ((1 << 3) - 1) +#define YT921X_SHAPE_BURST_MAX ((1 << 14) - 1) +#define YT921X_SHAPE_RATE_MAX ((1 << 18) - 1) #define YT921X_LAG_NUM 2 #define YT921X_LAG_PORT_NUM 4 @@ -578,7 +632,16 @@ enum yt921x_fdb_entry_status { #define YT921X_TAG_LEN 8 /* 8 internal + 2 external + 1 mcu */ -#define YT921X_PORT_NUM 11 +#define YT921X_PORT_NUM 11 +#define YT921X_UCAST_QUEUE_NUM 8 +#define YT921X_MCAST_QUEUE_NUM 4 +#define YT921X_PORT_QUEUE_NUM \ + (YT921X_UCAST_QUEUE_NUM + YT921X_MCAST_QUEUE_NUM) +#define YT921X_UCAST_QUEUE_ID(port, queue) \ + (YT921X_UCAST_QUEUE_NUM * (port) + (queue)) +#define YT921X_MCAST_QUEUE_ID(port, queue) \ + (YT921X_UCAST_QUEUE_NUM * YT921X_PORT_NUM + \ + YT921X_MCAST_QUEUE_NUM * (port) + (queue)) #define yt921x_port_is_internal(port) ((port) < 8) #define yt921x_port_is_external(port) (8 <= (port) && (port) < 9) @@ -657,6 +720,8 @@ struct yt921x_priv { const struct yt921x_info *info; unsigned int meter_slot_ns; + unsigned int port_shape_slot_ns; + unsigned int queue_shape_slot_ns; /* cache of dsa_cpu_ports(ds) */ u16 cpu_ports_mask; u8 cycle_ns; -- 2.51.0