From: Zong Li This patch implements .hw_info operation and the related data structures for passing the IOMMU hardware capabilities for iommufd. Signed-off-by: Zong Li Reviewed-by: Jason Gunthorpe Signed-off-by: Fangyu Yu --- drivers/iommu/riscv/iommu.c | 19 +++++++++++++++++++ include/uapi/linux/iommufd.h | 18 ++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index cb9d315e82ee..9abf446e1b85 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1556,8 +1556,27 @@ static void riscv_iommu_release_device(struct device *dev) kfree_rcu_mightsleep(info); } +static void *riscv_iommu_hw_info(struct device *dev, u32 *length, u32 *type) +{ + struct riscv_iommu_device *iommu = dev_to_iommu(dev); + struct iommu_hw_info_riscv_iommu *info; + + info = kzalloc_obj(*info); + if (!info) + return ERR_PTR(-ENOMEM); + + info->capability = iommu->caps; + info->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL); + + *length = sizeof(*info); + *type = IOMMU_HW_INFO_TYPE_RISCV_IOMMU; + + return info; +} + static const struct iommu_ops riscv_iommu_ops = { .of_xlate = riscv_iommu_of_xlate, + .hw_info = riscv_iommu_hw_info, .capable = riscv_iommu_capable, .identity_domain = &riscv_iommu_identity_domain, .blocked_domain = &riscv_iommu_blocking_domain, diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index e998dfbd6960..79d3dc5e8d19 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -660,6 +660,22 @@ struct iommu_hw_info_amd { __aligned_u64 efr2; }; +/** + * struct iommu_hw_info_riscv_iommu - RISCV IOMMU hardware information + * + * @capability: Value of RISC-V IOMMU capability register defined in + * RISC-V IOMMU spec section 5.3 IOMMU capabilities + * @fctl: Value of RISC-V IOMMU feature control register defined in + * RISC-V IOMMU spec section 5.4 Features-control register + * + * Don't advertise ATS support to the guest because driver doesn't support it. + */ +struct iommu_hw_info_riscv_iommu { + __aligned_u64 capability; + __u32 fctl; + __u32 __reserved; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hardware @@ -670,6 +686,7 @@ struct iommu_hw_info_amd { * @IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) info type * @IOMMU_HW_INFO_TYPE_AMD: AMD IOMMU info type + * @IOMMU_HW_INFO_TYPE_RISCV_IOMMU: RISC-V iommu info type */ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_NONE = 0, @@ -678,6 +695,7 @@ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_ARM_SMMUV3 = 2, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV = 3, IOMMU_HW_INFO_TYPE_AMD = 4, + IOMMU_HW_INFO_TYPE_RISCV_IOMMU = 5, }; /** -- 2.50.1