Add the gp_mn pin mux function on gpio35 of SA8775P. This exposes the GP M/N divider clock output on the dedicated GPIO pin. Reviewed-by: Konrad Dybcio Signed-off-by: Taniya Das --- drivers/pinctrl/qcom/pinctrl-sa8775p.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/qcom/pinctrl-sa8775p.c b/drivers/pinctrl/qcom/pinctrl-sa8775p.c index 5dbaa50cbff008a2605876eb329496d305735700..d299f47a0bd4ab1a0cd0e553ba50f9ec1e035686 100644 --- a/drivers/pinctrl/qcom/pinctrl-sa8775p.c +++ b/drivers/pinctrl/qcom/pinctrl-sa8775p.c @@ -480,6 +480,7 @@ enum sa8775p_functions { msm_mux_gcc_gp3, msm_mux_gcc_gp4, msm_mux_gcc_gp5, + msm_mux_gp_mn, msm_mux_hs0_mi2s, msm_mux_hs1_mi2s, msm_mux_hs2_mi2s, @@ -828,6 +829,10 @@ static const char * const gcc_gp5_groups[] = { "gpio34", "gpio42", }; +static const char * const gp_mn_groups[] = { + "gpio35", +}; + static const char * const hs0_mi2s_groups[] = { "gpio114", "gpio115", "gpio116", "gpio117", }; @@ -1230,6 +1235,7 @@ static const struct pinfunction sa8775p_functions[] = { MSM_PIN_FUNCTION(gcc_gp3), MSM_PIN_FUNCTION(gcc_gp4), MSM_PIN_FUNCTION(gcc_gp5), + MSM_PIN_FUNCTION(gp_mn), MSM_PIN_FUNCTION(hs0_mi2s), MSM_PIN_FUNCTION(hs1_mi2s), MSM_PIN_FUNCTION(hs2_mi2s), @@ -1361,7 +1367,7 @@ static const struct msm_pingroup sa8775p_groups[] = { [32] = PINGROUP(32, qup0_se4, phase_flag, _, _, _, _, _, _, _), [33] = PINGROUP(33, qup0_se4, gcc_gp4, _, ddr_pxi0, _, _, _, _, _), [34] = PINGROUP(34, qup0_se4, gcc_gp5, _, ddr_pxi0, _, _, _, _, _), - [35] = PINGROUP(35, qup0_se4, phase_flag, _, _, _, _, _, _, _), + [35] = PINGROUP(35, qup0_se4, phase_flag, gp_mn, _, _, _, _, _, _), [36] = PINGROUP(36, qup0_se2, qup0_se5, phase_flag, tgu_ch2, _, _, _, _, _), [37] = PINGROUP(37, qup0_se2, qup0_se5, phase_flag, tgu_ch3, _, _, _, _, _), [38] = PINGROUP(38, qup0_se5, qup0_se2, qdss_cti, phase_flag, tgu_ch4, _, _, _, _), -- 2.34.1