The MaxLinear GSW1xx family got a single (R)(G)MII port at index 5 but the registers MII_PCDU and MII_CFG are those of port 0. Allow applying an offset for the port index to access those registers. Signed-off-by: Daniel Golle --- v2: no changes drivers/net/dsa/lantiq/lantiq_gswip.c | 12 ++++++++++-- drivers/net/dsa/lantiq/lantiq_gswip.h | 1 + 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.c b/drivers/net/dsa/lantiq/lantiq_gswip.c index 3e2a54569828..64e378852284 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.c +++ b/drivers/net/dsa/lantiq/lantiq_gswip.c @@ -183,21 +183,29 @@ static void gswip_mii_mask(struct gswip_priv *priv, u32 clear, u32 set, static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set, int port) { + int reg_port; + /* MII_CFG register only exists for MII ports */ if (!(priv->hw_info->mii_ports & BIT(port))) return; - gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port)); + reg_port = port + priv->hw_info->mii_port_reg_offset; + + gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(reg_port)); } static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set, int port) { + int reg_port; + /* MII_PCDU register only exists for MII ports */ if (!(priv->hw_info->mii_ports & BIT(port))) return; - switch (port) { + reg_port = port + priv->hw_info->mii_port_reg_offset; + + switch (reg_port) { case 0: gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0); break; diff --git a/drivers/net/dsa/lantiq/lantiq_gswip.h b/drivers/net/dsa/lantiq/lantiq_gswip.h index 19bbe6fddf04..2df9c8e8cfd0 100644 --- a/drivers/net/dsa/lantiq/lantiq_gswip.h +++ b/drivers/net/dsa/lantiq/lantiq_gswip.h @@ -233,6 +233,7 @@ struct gswip_hw_info { int max_ports; unsigned int allowed_cpu_ports; unsigned int mii_ports; + int mii_port_reg_offset; const struct gswip_pce_microcode (*pce_microcode)[]; size_t pce_microcode_size; enum dsa_tag_protocol tag_protocol; -- 2.51.0