| 2026-02-27 09:13 UTC |
avoid compiler and IQ/OQ reordering |
2 |
vimleshk@marvell.com |
finished
in 1h18m0s
|
| 2026-02-12 12:16 UTC |
avoid compiler and IQ/OQ reordering |
1 |
vimleshk@marvell.com |
finished
in 1h6m0s
|
| 2026-02-06 11:15 UTC |
disable interrupts and ensure dbell updation |
4 |
vimleshk@marvell.com |
finished
in 47m0s
|
| 2026-01-30 14:15 UTC |
disable interrupts and ensure dbell updation |
3 |
vimleshk@marvell.com |
finished
in 1h3m0s
|
| 2026-01-15 09:20 UTC |
octeon_ep: reset firmware ready status |
4 |
vimleshk@marvell.com |
finished
in 1h3m0s
|
| 2026-01-07 13:45 UTC |
octeon_ep: reset firmware ready status |
3 |
vimleshk@marvell.com |
finished
in 51m0s
|
| 2026-01-07 13:18 UTC |
disable interrupts and ensure dbell updation |
3 |
vimleshk@marvell.com |
finished
in 54m0s
|
| 2025-12-19 10:07 UTC |
disable interrupts and ensure dbell updation |
2 |
vimleshk@marvell.com |
finished
in 50m0s
|
| 2025-12-19 07:29 UTC |
avoid compiler and IQ/OQ reordering |
1 |
vimleshk@marvell.com |
finished
in 55m0s
|
| 2025-12-12 12:23 UTC |
disable interrupts and ensure dbell updation |
1 |
vimleshk@marvell.com |
finished
in 52m0s
|
| 2025-12-05 09:10 UTC |
octeon_ep: reset firmware ready status |
2 |
vimleshk@marvell.com |
finished
in 51m0s
|
| 2025-11-20 11:23 UTC |
octeon_ep: reset firmware ready status |
1 |
vimleshk@marvell.com |
finished
in 1h2m0s
|