| 2026-09-21 11:13 UTC |
KVM: riscv: Age G-stage PTEs locklessly |
1 |
suunj1331@gmail.com |
-
|
| 2026-09-18 07:26 UTC |
KVM: riscv: Age all G-stage PTEs in a GFN range |
1 |
suunj1331@gmail.com |
skipped
|
| 2026-08-15 10:31 UTC |
KVM: riscv: Add KVM_PRE_FAULT_MEMORY support |
4 |
jinyu.tang@linux.dev |
finished
in 1h7m0s
|
| 2026-08-15 10:00 UTC |
KVM: riscv: Add KVM_PRE_FAULT_MEMORY support |
4 |
jinyu.tang@linux.dev |
finished
in 1h37m0s
|
| 2026-08-14 12:35 UTC |
KVM: riscv: Avoid redundant interrupt check for pending timers |
1 |
jinyu.tang@linux.dev |
finished
in 1h45m0s
|
| 2026-08-14 11:45 UTC |
KVM: riscv: Add KVM_PRE_FAULT_MEMORY support |
3 |
jinyu.tang@linux.dev |
finished
in 1h14m0s
|
| 2026-08-14 10:57 UTC |
KVM: riscv: Avoid overwriting existing G-stage tables with huge leaves |
1 |
jinyu.tang@linux.dev |
finished
in 1h55m0s
|
| 2026-08-11 23:03 UTC |
KVM: riscv: Add KVM_PRE_FAULT_MEMORY support |
2 |
jinyu.tang@linux.dev |
finished
in 1h30m0s
|
| 2026-08-11 06:01 UTC |
KVM: riscv: Add KVM_PRE_FAULT_MEMORY support |
1 |
jinyu.tang@linux.dev |
finished
in 1h30m0s
|
| 2026-08-10 10:18 UTC |
KVM: RISC-V: Add CPU PM notifier for non-retention idle states |
5 |
yongxuan.wang@sifive.com |
skipped
|
| 2026-07-22 05:52 UTC |
KVM: RISC-V: Add CPU PM notifier for non-retention idle states |
4 |
yongxuan.wang@sifive.com |
finished
in 2h25m0s
|
| 2026-07-01 14:26 UTC |
PCI bus/CPU address translation for MMIO |
1 |
tjytimi@163.com |
skipped
|
| 2026-06-26 09:38 UTC |
KVM: RISC-V: Add CPU PM notifier for non-retention idle states |
3 |
yongxuan.wang@sifive.com |
finished
in 1h41m0s
|
| 2026-06-26 08:23 UTC |
KVM: RISC-V: Add CPU PM notifier for non-retention idle states |
2 |
yongxuan.wang@sifive.com |
finished
in 1h29m0s
|
| 2026-06-04 14:26 UTC |
KVM: riscv: Fix hugetlb G-stage block mapping eligibility |
2 |
tjytimi@163.com |
finished
in 1h36m0s
|
| 2026-05-20 15:21 UTC |
KVM: riscv: Fix hugetlb G-stage block mapping eligibility |
1 |
tjytimi@163.com |
finished
in 1h39m0s
|
| 2026-05-17 15:34 UTC |
KVM: riscv: Speed up dirty logging write faults |
1 |
tjytimi@163.com |
finished
in 1h19m0s
|
| 2026-04-12 02:38 UTC |
RISC-V: KVM: Batch stage-2 TLB flushes |
4 |
tjytimi@163.com |
finished
in 55m0s
|
| 2026-04-08 16:11 UTC |
RISC-V: KVM: Batch stage-2 remote TLB flushes |
3 |
tjytimi@163.com |
finished
in 1h19m0s
|
| 2026-03-18 12:35 UTC |
RISC-V: KVM: Batch stage-2 remote TLB flushes |
2 |
tjytimi@163.com |
finished
in 1h1m0s
|
| 2026-03-07 13:04 UTC |
RISC-V: KVM: Batch stage-2 remote TLB flushes |
1 |
tjytimi@163.com |
finished
in 1h12m0s
|
| 2026-02-27 12:10 UTC |
KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core |
7 |
tjytimi@163.com |
finished
in 1h22m0s
|
| 2026-02-26 12:38 UTC |
KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core |
6 |
tjytimi@163.com |
finished
in 1h17m0s
|
| 2026-02-25 03:14 UTC |
KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core |
5 |
tjytimi@163.com |
finished
in 55m0s
|
| 2026-02-22 04:57 UTC |
KVM: riscv: Skip CSR restore if VCPU is reloaded on the same core |
4 |
tjytimi@163.com |
finished
in 53m0s
|
| 2025-09-15 15:27 UTC |
kvm/riscv: Add ctxsstatus and ctxhstatus for migration |
1 |
tjytimi@163.com |
finished
in 1h43m0s
|
| 2025-09-15 12:23 UTC |
KVM: riscv: Power on secondary vCPUs from migration |
1 |
tjytimi@163.com |
finished
in 48m0s
|
| 2025-08-25 12:14 UTC |
riscv: skip csr restore if vcpu preempted reload |
3 |
tjytimi@163.com |
finished
in 37m0s
|
| 2025-08-25 11:07 UTC |
riscv: skip csr restore if vcpu preempted reload |
2 |
tjytimi@163.com |
finished
in 36m0s
|
| 2025-08-07 11:42 UTC |
riscv: skip csr restore if vcpu preempted reload |
1 |
tjytimi@163.com |
finished
in 1h5m0s
|