| 2025-11-30 13:16 UTC |
DSA simple HSR offload |
1 |
vladimir.oltean@nxp.com |
finished
in 3h52m0s
|
| 2025-11-27 12:08 UTC |
Introduce the dsa_xmit_port_mask() tagging protocol helper |
1 |
vladimir.oltean@nxp.com |
finished
in 1h42m0s
|
| 2025-11-21 11:35 UTC |
Add ETHSW support for Renesas RZ/T2H and RZ/N2H SoCs |
1 |
prabhakar.csengg@gmail.com |
finished
in 56m0s
|
| 2025-11-12 20:19 UTC |
Add support for PHY link active-level configuration in RZN1 MIIC driver |
1 |
prabhakar.csengg@gmail.com |
finished
in 49m0s
|
| 2025-09-10 20:41 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
3 |
prabhakar.csengg@gmail.com |
finished
in 43m0s
|
| 2025-09-04 11:41 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
2 |
prabhakar.csengg@gmail.com |
finished
in 52m0s
|
| 2025-09-01 22:43 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
1 |
prabhakar.csengg@gmail.com |
skipped
|
| 2025-09-01 11:20 UTC |
net: pcs: rzn1-miic: Correct MODCTRL register offset |
3 |
prabhakar.csengg@gmail.com |
finished
in 58m0s
|
| 2025-08-20 17:09 UTC |
net: pcs: rzn1-miic: Correct MODCTRL register offset |
2 |
prabhakar.csengg@gmail.com |
finished
in 37m0s
|
| 2025-08-18 15:07 UTC |
net: pcs-rzn1-miic: Correct MODCTRL register offset |
1 |
prabhakar.csengg@gmail.com |
finished
in 1h55m0s
|
| 2025-07-07 00:39 UTC |
net: dsa: rzn1_a5psw: add COMPILE_TEST |
1 |
rosenp@gmail.com |
finished
in 4h53m0s
|