| 2026-10-14 15:32 UTC |
net: pcs: rzn1-miic: Validate dtb configuration values |
4 |
devnull@kernel.org |
skipped
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| 2026-10-14 13:18 UTC |
Add ETHSW support for Renesas RZ/T2H and RZ/N2H SoCs |
3 |
prabhakar.csengg@gmail.com |
skipped
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| 2026-10-06 16:48 UTC |
net: pcs: rzn1-miic: Validate dtb configuration values |
3 |
devnull@kernel.org |
skipped
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| 2026-10-01 15:43 UTC |
Add ETHSW support for Renesas RZ/T2H and RZ/N2H SoCs |
2 |
prabhakar.csengg@gmail.com |
skipped
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| 2026-09-28 21:19 UTC |
net: pcs: rzn1-miic: Validate dtb configuration values |
2 |
devnull@kernel.org |
skipped
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| 2026-09-25 15:12 UTC |
net: pcs: rzn1-miic: Validate dtb configuration values |
1 |
devnull@kernel.org |
skipped
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| 2026-09-24 10:36 UTC |
net: pcs: rzn1-miic: Clear MIIC protection state before unprotect sequence |
4 |
yoshihisa.yamamoto.xn@renesas.com |
skipped
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| 2026-09-18 04:30 UTC |
net: pcs: rzn1-miic: Reset PRCMD state before unprotect sequence |
3 |
yoshihisa.yamamoto.xn@renesas.com |
finished
in 1h3m0s
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| 2026-09-17 02:49 UTC |
net: pcs: rzn1-miic: Reset PRCMD state before unprotect sequence |
2 |
yoshihisa.yamamoto.xn@renesas.com |
skipped
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| 2026-09-16 02:39 UTC |
net: pcs: rzn1-miic: Reset PRCMD state before unprotect sequence |
1 |
yoshihisa.yamamoto.xn@renesas.com |
skipped
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| 2026-09-15 17:39 UTC |
net: pcs: rzn1-miic: Fix config array initialization |
5 |
devnull@kernel.org |
skipped
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| 2026-09-14 16:41 UTC |
net: pcs: rzn1-miic: Fix config array initialization |
4 |
devnull@kernel.org |
skipped
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| 2026-09-14 15:56 UTC |
dt-bindings: net: Use consistent indentation in the example |
2 |
krzysztof.kozlowski@oss.qualcomm.com |
skipped
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| 2026-09-13 12:29 UTC |
dt-bindings: net: Use consistent indentation in the example |
1 |
krzysztof.kozlowski@oss.qualcomm.com |
skipped
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| 2026-09-04 04:36 UTC |
Remove comma after sentinel entries in match table |
1 |
s-vadapalli@ti.com |
skipped
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| 2026-09-02 18:37 UTC |
net: pcs: rzn1-miic: Fix config array initialization |
3 |
devnull@kernel.org |
skipped
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| 2026-09-01 15:25 UTC |
net: pcs: rzn1-miic: Fix config array initialization |
2 |
devnull@kernel.org |
skipped
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| 2026-08-13 18:05 UTC |
net: pcs: rzn1-miic: Fix config array initialization |
1 |
devnull@kernel.org |
finished
in 59m0s
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| 2026-06-25 07:47 UTC |
net: dsa: Fix skb ownership in taggers |
5 |
linusw@kernel.org |
finished
in 4h26m0s
|
| 2026-06-22 12:47 UTC |
net: dsa: Fix skb ownership in taggers |
4 |
linusw@kernel.org |
finished
in 4h40m0s
|
| 2026-06-17 12:30 UTC |
net: dsa: Fix skb ownership in taggers |
3 |
linusw@kernel.org |
finished
in 4h51m0s
|
| 2026-06-16 09:36 UTC |
net: dsa: Fix skb ownership in taggers |
2 |
linusw@kernel.org |
finished
in 3h53m0s
|
| 2026-06-15 22:33 UTC |
net: dsa: Fix skb ownership in taggers |
1 |
linusw@kernel.org |
finished
in 4h59m0s
|
| 2026-01-12 17:35 UTC |
net: pcs: rzn1-miic: Support configurable PHY_LINK polarity |
3 |
prabhakar.csengg@gmail.com |
finished
in 1h12m0s
|
| 2026-01-09 14:22 UTC |
Add support for PHY link active-level configuration in RZN1 MIIC driver |
2 |
prabhakar.csengg@gmail.com |
finished
in 57m0s
|
| 2025-11-30 13:16 UTC |
DSA simple HSR offload |
1 |
vladimir.oltean@nxp.com |
finished
in 3h52m0s
|
| 2025-11-27 12:08 UTC |
Introduce the dsa_xmit_port_mask() tagging protocol helper |
1 |
vladimir.oltean@nxp.com |
finished
in 1h42m0s
|
| 2025-11-21 11:35 UTC |
Add ETHSW support for Renesas RZ/T2H and RZ/N2H SoCs |
1 |
prabhakar.csengg@gmail.com |
finished
in 56m0s
|
| 2025-11-12 20:19 UTC |
Add support for PHY link active-level configuration in RZN1 MIIC driver |
1 |
prabhakar.csengg@gmail.com |
finished
in 49m0s
|
| 2025-09-10 20:41 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
3 |
prabhakar.csengg@gmail.com |
finished
in 43m0s
|
| 2025-09-04 11:41 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
2 |
prabhakar.csengg@gmail.com |
finished
in 52m0s
|
| 2025-09-01 22:43 UTC |
Add PCS support for Renesas RZ/{T2H,N2H} SoCs |
1 |
prabhakar.csengg@gmail.com |
skipped
|
| 2025-09-01 11:20 UTC |
net: pcs: rzn1-miic: Correct MODCTRL register offset |
3 |
prabhakar.csengg@gmail.com |
finished
in 58m0s
|
| 2025-08-20 17:09 UTC |
net: pcs: rzn1-miic: Correct MODCTRL register offset |
2 |
prabhakar.csengg@gmail.com |
finished
in 37m0s
|
| 2025-08-18 15:07 UTC |
net: pcs-rzn1-miic: Correct MODCTRL register offset |
1 |
prabhakar.csengg@gmail.com |
finished
in 1h55m0s
|
| 2025-07-07 00:39 UTC |
net: dsa: rzn1_a5psw: add COMPILE_TEST |
1 |
rosenp@gmail.com |
finished
in 4h53m0s
|